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Chipcon
SmartRF a CC1010
CC1010 Single Chip Very Low Power RF Transceiver with 8051-Compatible Microcontroller
Applications
* Very low power UHF wireless data transmitters and receivers * 315 / 433 / 868 and 915 MHz ISM/SRD band systems * Home automation and security * AMR - Automatic Meter Reading * RKE - Remote Keyless Entry with acknowledgement * Low power telemetry * Toys
Product Description
The CC1010 is a true single-chip UHF transceiver with an integrated high performance 8051 microcontroller with 32 kB of Flash program memory. The RF transceiver can be programmed for operation in the 300 - 1000 MHz range, and is designed for very low power wireless applications. The CC1010 together with a few external passive components constitutes a powerful embedded system with wireless communication capabilities.
CC1010 is SmartRFa02 CMOS.
based on technology in
Chipcon's 0.35 m
Key Features
* 300-1000 MHz RF Transceiver * Very low current consumption * High sensitivity (typically -107 dBm) * Programmable output power up to +10 dBm * Data rate up to 76.8 kbit/s * Very few external components * Fast PLL settling allowing frequency hopping protocols * RSSI * EN 300 220 and FCC CFR47 part 15 compliant * 8051-Compatible Microcontroller * Typically 2.5 times the performance of a standard 8051 * 32 kB Flash, 2048 + 128 Byte SRAM * 3 channel 10 bit ADC, 4 timers / 2 PWMs, 2 UARTs, RTC, Watchdog, SPI, DES encryption, 26 general I/O pins * In-circuit interactive debugging is supported for the Keil Vision2 IDE through a simple serial interface. * 2.7 - 3.6 V supply voltage * 64-lead TQFP
This document contains information on a preproduction product. Specifications and information herein are subject to change without notice.
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 1 of 133
Chipcon
Table Of Contents
SmartRF a CC1010
FEATURES ............................................................................................................................................ 4 ABSOLUTE MAXIMUM RATINGS .................................................................................................. 5 RECOMMENDED OPERATING CONDITIONS............................................................................. 5 DC CHARACTERISTICS.................................................................................................................... 6 ELECTRICAL SPECIFICATIONS .................................................................................................... 7 PIN CONFIGURATION..................................................................................................................... 11 PIN DESCRIPTION............................................................................................................................ 13 BLOCK DIAGRAM ............................................................................................................................ 16 8051 CORE........................................................................................................................................... 17 GENERAL DESCRIPTION ...................................................................................................................... 17 RESET ................................................................................................................................................. 17 MEMORY MAP.................................................................................................................................... 18 CPU REGISTERS ................................................................................................................................. 21 INSTRUCTION SET SUMMARY ............................................................................................................. 22 INTERRUPTS........................................................................................................................................ 26 MAIN CRYSTAL OSCILLATOR ............................................................................................................. 30 POWER AND CLOCK MODES ............................................................................................................... 31 FLASH PROGRAM MEMORY ................................................................................................................ 34 SPI FLASH PROGRAMMING................................................................................................................. 34 8051 FLASH PROGRAMMING .............................................................................................................. 39 FLASH POWER CONTROL .................................................................................................................... 40 IN CIRCUIT DEBUGGING ..................................................................................................................... 41 CHIP VERSION / REVISION .................................................................................................................. 42 8051 PERIPHERALS .......................................................................................................................... 43 GENERAL PURPOSE I/O....................................................................................................................... 43 TIMER 0 / TIMER 1.............................................................................................................................. 48 TIMER 2 / 3 WITH PWM ..................................................................................................................... 54 POWER ON RESET (BROWN-OUT DETECTION) ................................................................................... 57 WATCHDOG TIMER............................................................................................................................. 58 REALTIME CLOCK............................................................................................................................... 61 SERIAL PORT 0 AND 1 ......................................................................................................................... 62 SPI MASTER ....................................................................................................................................... 67 DES ENCRYPTION / DECRYPTION....................................................................................................... 70 RANDOM BIT GENERATION ................................................................................................................ 74 ADC................................................................................................................................................... 75 RF TRANSCEIVER ............................................................................................................................ 78 GENERAL DESCRIPTION ...................................................................................................................... 78 RF TRANSCEIVER BLOCK DIAGRAM .................................................................................................. 78 RF APPLICATION CIRCUIT .................................................................................................................. 80 TRANSCEIVER CONFIGURATION OVERVIEW ....................................................................................... 83 RF TRANSCEIVER RX/TX CONTROL AND POWER MANAGEMENT ....................................................... 84 DATA MODEM AND DATA MODES...................................................................................................... 86 BAUDRATES........................................................................................................................................ 89 TRANSMITTING AND RECEIVING DATA................................................................................................ 90 DEMODULATION AND DATA DECISION ................................................................................................ 92 SYNCHRONIZATION AND PREAMBLE DETECTION ................................................................................ 96 RECEIVER SENSITIVITY VERSUS DATA RATE AND FREQUENCY SEPARATION ....................................... 99 FREQUENCY PROGRAMMING............................................................................................................. 100 LOCK INDICATION ............................................................................................................................ 102 RECOMMENDED SETTINGS FOR ISM FREQUENCIES.......................................................................... 103 VCO................................................................................................................................................. 105
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 2 of 133
Chipcon
SmartRF a CC1010
VCO AND PLL SELF-CALIBRATION .................................................................................................. 105 VCO, LNA AND BUFFER CURRENT CONTROL................................................................................... 110 INPUT / OUTPUT MATCHING ............................................................................................................. 112 OUTPUT POWER PROGRAMMING ...................................................................................................... 113 RSSI OUTPUT................................................................................................................................... 115 IF OUTPUT ....................................................................................................................................... 116 OPTIONAL LC FILTER....................................................................................................................... 117 RESERVED REGISTERS AND TEST REGISTERS..................................................................................... 118 SYSTEM CONSIDERATIONS AND GUIDELINES.................................................................................... 120 PCB LAYOUT RECOMMENDATIONS.................................................................................................. 122 ANTENNA CONSIDERATIONS ............................................................................................................ 122 PACKAGE DESCRIPTION (TQFP-64) ......................................................................................... 123 SOLDERING INFORMATION....................................................................................................... 124 TRAY SPECIFICATION ................................................................................................................. 124 CARRIER TAPE AND REEL SPECIFICATION ......................................................................... 124 LIST OF ABBREVIATIONS ........................................................................................................... 125 SFR SUMMARY................................................................................................................................ 126 ALPHABETIC REGISTER INDEX................................................................................................ 130 ORDERING INFORMATION......................................................................................................... 133
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 3 of 133
Chipcon
Features
* Fully Integrated UHF RF Transceiver * Programmable frequency in the range 300 - 1000 MHz * High sensitivity (typically -107 dBm at 2.4 kBaud) * Programmable output power -20 to +10 dBm * Very low current consumption (RX: 9.1 mA) * Very few external components required and no external RF switch or IF filter required * Single port antenna connection * Fast PLL settling allows frequency hopping protocols * FSK modulation with a data rate of up to 76.8 kBaud * Manchester or NRZ coding and decoding of data performed in hardware. Byte delineation of data can be performed in hardware to lessen the processor burden * RSSI output which can be sampled by on-chip ADC * Complies with EN 300 220 and FCC CFR47 part 15 * High-Performance and Low-Power 8051-Compatible Microcontroller * Optimised 8051-core which typically gives 2.5x the performance of a standard 8051 * Dual data pointers * Idle and sleep modes * In-circuit interactive debugging is supported for the Keil Vision IDE through a simple serial interface * Data and Nonvolatile Program Memory * 32 kB of nonvolatile Flash memory in-system programmable through a simple SPI interface or by the 8051 core. * Typical Flash memory endurance: 20 000 write/erase cycles
SmartRF a CC1010
*
*
*
*
*
* Programmable read and write lock of portions of Flash memory for software security * 2048 + 128 Byte of internal SRAM Hardware DES Encryption / Decryption * DES supported in hardware * Output Feedback Mode or Cipher Feedback Mode DES to avoid the requirement that data length must be a multiple of eight bytes Peripheral Features * Power On Reset / Brown-Out Detection * Three channel, max 23 kSample/s, 10 bit ADC * Programmable watchdog timer. * Real time clock with 32 kHz crystal oscillator * Two timers / pulse counters and two timers / pulse width modulators * Two programmable serial UARTs. * Master SPI interface * 26 configurable general-purpose I/O-pins * Random bit generator in hardware Low Power * 8051 core and peripherals can use the RTC's 32 kHz clock * Idle and sleep modes for reduced power consumption. System can wake up on interrupt or when ADC input exceeds a set threshold * Low-power fully static CMOS design Operating Conditions * 2.7 - 3.6 V supply voltage * -40 - 85 C operational temperature * 3 - 24 MHz crystal (up to 50 ppm) for the main crystal oscillator Packaging * 64-lead TQFP
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 4 of 133
Chipcon
Absolute Maximum Ratings
SmartRF a CC1010
Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device. Table 1. Absolute Maximum Ratings
Parameter Supply voltage, VDD Voltage on any pin Input RF level Storage temperature range Storage temperature range Lead temperature Min. -0.3 -0.3 -50 -40 Max. 5.0 VDD+0.3, max 5.0 10 150 125 260 Units V V dBm C C C Condition
Un-programmed device Programmed device, data retention > 0.49 years at 125C T = 10 s
Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage.
Recommended Operating Conditions
Table 2. Recommended Operating Conditions
Tc = -40 to 85C, VDD = 2.7 to 3.6 V if nothing else stated
Parameter Supply voltage, DVDD, AVDD
Min
Typ 3.3
Max
Unit V
Condition Supply voltage during normal operation Supply voltage during program/erase Flash memory
2.7 Supply voltage, DVDD, AVDD 2.7
3.6 3.6
V V
Operating temperature, free-air Main oscillator frequency RTC oscillator frequency
-40 3 32768
85 24
C MHz kHz
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 5 of 133
Chipcon
DC Characteristics
SmartRF a CC1010
The DC Characteristics of CC1010 are listed in Table 3 below. Table 3. DC Characteristics
Tc = 25C, VDD = 3.3 V if nothing else stated
Digital Inputs/Outputs Logic "0" input voltage Logic "1" input voltage Logic "0" output voltage
Min 0 0.7*VDD 0
Typ
Max 0.3*VDD VDD 0.4
Unit V V V
Condition
Logic "1" output voltage
2.5
VDD
V
Logic "0" output voltage Logic "1" output voltage Logic "0" input current Logic "1" input current
0 2.5 NA NA
0.4 VDD -1 1
V V A A
Output current -2.0 mA, ports P0.3-P0.0, P1.7P1.0, P2.7-P2.4, P2.2P2.0 Output current 2.0mA, ports P0.3-P0.0, P1.7P1.0, P2.7-P2.4, P2.2P2.0 Output current -8.0 mA, port P2.3 Output current 8.0mA, port P2.3 Input signal equals GND Input signal equals VDD
25
Supply current [mA]
20 15 10 5 0 0 4 8 12 Frequency [MHz] 16 20 24
Figure 1. Typical CPU core supply current vs. clock frequency
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 6 of 133
Chipcon
Electrical Specifications
Table 4. Electrical Specifications
Tc = 25C, VDD = 3.3 V if nothing else stated
SmartRF a CC1010
Parameter MCU, general Power on reset (POR) voltage Brown out voltage RTC start-up time ADC, number of bits ADC, Differential Nonlinearity (DNL) ADC, Integral Nonlinearity (INL) ADC, Offset ADC, Total Harmonic Distortion (THD) ADC, SINAD ADC, internal reference tolerance Supply Current MCU, Active mode
Min.
Typ.
Max.
Unit
Condition
2.7 2.7
2.9 2.9 160 10 +/-0.2 +/-1.3 3 59 54 9 10
3.1 3.1
V V ms bits LSB LSB LSB dB dB bits %
Tc = -40 to 85C Tc = -40 to 85C
VDD is reference voltage VDD is reference voltage 7 Hz test tone 7 Hz test tone 7 Hz test tone
14.8 1.3
mA mA
14.7456 MHz, main oscillator 32 kHz, RTC oscillator See page 31 for explanation of modes. See Figure 1 page 6 for supply current vs. clock frequency. 14.7456 MHz, main oscillator 32 kHz, RTC oscillator
MCU, Idle mode MCU, Power Down mode
8.2 29.4 0.2 10
mA A A
RF Transceiver, Receive mode, 433/868 MHz
9.1/ 11.9
mA
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 7 of 133
Chipcon
Parameter RF Transceiver, Transmit mode, 433/868 MHz
P=0.01 mW (-20 dBm) P=0.3 mW (-5 dBm) P=1 mW (0 dBm) P=2.5 mW (4 dBm) P=10 mW (10 dBm) 5.3/8.6 8.9/13.8 10.4/17 24.8/ 23.5 26.6/NA
SmartRF a CC1010
Min. Typ. Max. Unit Condition The output power is delivered to a 50 load, see also page 113.
mA mA mA mA mA
RF Transceiver, Power Down mode RF Transceiver, general RF Frequency Range Transmit Section Transmit data rate 0.6 300
0.2
1
A
1000
MHz
Programmable in steps of < 250 Hz
78.6
kBaud
Binary FSK frequency separation
0
64
65
kHz
NRZ or Manchester encoding. 76.8 kBaud equals 76.8 kbit/s using NRZ coding. See page 89. The frequency corresponding to the digital "0" is denoted f0, while f1 corresponds to a digital "1". The frequency separation is f1-f0. The RF carrier frequency, fc, is then given by fc=(f0+f1)/2. (The frequency deviation is given by fd=+/-(f1-f0)/2 ) The frequency separation is programmable in 250 Hz steps. 65 kHz is the minimum guaranteed separation at 1 MHz reference frequency. Larger separations can be achieved at higher reference frequencies. Delivered to 50 load. The output power is programmable, see page 113. Transmit mode, optimum load impedance. For matching details see "Input/ output matching" p.112.
Output power 433 / 868 MHz RF output impedance 433 / 868 MHz
-20
0
10/4
dBm
140/80
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 8 of 133
Chipcon
Parameter Harmonics Min. Typ. -25
SmartRF a CC1010
Max. Unit dBc Condition An external LC filter should be used to reduce harmonics emission to comply with SRD requirements. See p.117.
Receive Section Receiver Sensitivity, 433 / 868 MHz -107/ -106 dBm 2.4 kBaud, Manchester coded data, 64 kHz frequency -3 separation, BER = 10 See Table 25 and Table 26 page 99 for typical sensitivity figures at other data rates. System noise bandwidth Cascaded noise figure 433/868 MHz Saturation (maximum input level) Input IP3 Blocking LO leakage Input impedance 90-j13 68-j24 36-j11 36-j13 10 -26 40 -57 30 12/13 kHz dB dBm dBm dBc dBm Receive mode, series equivalent at 315 MHz at 433 MHz at 868 MHz at 915 MHz For matching details see "Input/ output matching" p. 112. Turn on time 11 128 Baud The demodulator settling time, which is programmable, determines the turn-on time. See page 92 for details. 2.4 kBaud, Manchester coded -3 data, BER = 10 From LNA to IF output At +/- 1 MHz 2.4 kBaud, Manchester coded data
IF Section Intermediate frequency (IF) 433/868 MHz IF bandwidth (noise bandwidth) RSSI dynamic range -105 150/ 130 10.7 175 -60 kHz MHz kHz dBm Internal IF filter External IF filter
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 9 of 133
Chipcon
Parameter RSSI accuracy RSSI linearity Frequency Synthesiser Section Crystal Oscillator Frequency 3 Min. Typ. 6 2
SmartRF a CC1010
Max. Unit dB dB Condition See p. 115 for details
24
MHz
Crystal frequency can be 3-4, 6-8 or 9-24 MHz. Recommended frequencies are 3.6864, 7.3728, 11.0592, 14.7456, 18.4320 and 22.1184 MHz. See page 30 for details. 433 MHz 868 MHz The crystal frequency accuracy and drift (ageing and temperature dependency) will determine the frequency accuracy of the transmitted signal. C171 and C181 are loading capacitors
Crystal frequency accuracy requirement
50 25
ppm
Crystal operation Crystal load capacitance 12 12 12 12
Parallel 20 16 16 12 5 1.5 2 -85 200 250 30 30 16 16 pF pF pF pF ms ms ms dBc/Hz s s
3-4 MHz, 20 pF recommended 6-8 MHz, 16 pF recommended 9-16 MHz, 16 pF recommended 16-24 MHz, 12 pF recommended
Crystal oscillator start-up time
3.6864 MHz, 16 pF load 7.3728 MHz, 16 pF load 16 MHz, 16 pF load At 100 kHz offset from carrier
Output signal phase noise PLL lock time (RX / TX turn time) PLL turn-on time
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 10 of 133
Chipcon
Pin Configuration
AD2 (RSSI/IF) (Top view)
SmartRF a CC1010
P0_2 (MISO)
RESET
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD 1 AVDD 2 AGND 3 RF_IN 4 RF_OUT 5 AVDD 6 AGND 7 AGND 8 AGND 9 L1 10 L2 11 AVDD 12 CHP_OUT 13 R_BIAS 14 AVDD 15 AGND 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 XOSC_Q1 XOSC_Q2 (RXD1) P2_0 (TXD1) P2_1 XOSC32_Q2 XOSC32_Q1 (INT1) P3_3 POR_E AGND AGND DGND DGND P1_0 (PWM3) P3_5 (PWM2) P3_4 DGND 48 P3_0 (RXD0) 47 P3_1 (TXD0) 46 P3_2 (INT0) 45 P2_5 44 P2_4 43 DVDD
CC1010
DGND 42 P2_3 41 DGND 40 DVDD 39 P2_2 38 P1_4 37 P1_3 36 P1_2 35 P1_1 34 P0_1 (MOSI) 33 P0_0 (SCK)
PROG
AGND
DVDD
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Pin name AVDD AVDD AGND RF_IN RF_OUT AVDD AGND AGND AGND L1 L2 AVDD CHP_OUT R_BIAS AVDD AGND AGND
Alternate function -
Pin type Power (A) Power (A) Power (A) RF input RF output Power (A) Power (A) Power (A) Power (A) Analog Analog Power (A) Analog output Analog Power (A) Power (A) Power (A)
Description Power supply ADC Power supply Mixer and IF Ground connection Mixer and IF RF signal input from antenna (external ACcoupling) RF signal output to antenna Power supply LNA and PA Ground connection LNA and PA Ground connection PA Ground connection VCO and prescaler Connection #1 for external VCO tank inductor Connection #2 for external VCO tank inductor Power supply VCO and prescaler Charge pump current output when external loop filter is used Connection for external precision bias resistor (82 k, 1%) Power supply misc. analog modules Ground connection misc. analog modules Analog ground connection
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
DVDD
P2_7
P2_6
P1_7
P1_6
P1_5
P0_3
AD1
AD0
Page 11 of 133
Chipcon
Pin # 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Pin name XOSC_Q1 XOSC_Q2 XOSC32_Q 2 XOSC32_Q 1 AGND DGND DGND POR_E P1.0 P2.0 P2.1 P3.5 P3.4 P3.3 DGND P0.0 P0.1 P1.1 P1.2 P1.3 P1.4 P2.2 DVDD DGND P2.3 DVDD P2.4 P2.5 P3.2 P3.1 P3.0 DGND DVDD P0.2 P0.3 P1.5 P1.6 Alternate function RXD1 (I) TXD1 (O) PWM3 (O) T1 (I) PWM2 (O) T0 (I)
INT1 (I)
SmartRF a CC1010
Pin type Analog input Analog output Analog output Analog input Power (A) Power (D) Power (D) Digital input Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O Power (D) Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O (Schmitt trigger input) Power (D) Power (D) Digital high-Z I/O (8 mA) Power (D) Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O Power (D) Power (D) Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O Description 3-24 MHz crystal, pin 1 or external clock input 3-24 MHz crystal, pin 2 32 kHz crystal pin2 32 kHz crystal pin1 or external clock input Analog ground connection Digital ground connection Digital ground connection Power-on reset enable. 0: Disable internal power-on reset module 1: Enable internal power-on reset module 8051 port 1, bit 0 8051 port 2, bit 0 or RX of serial port 1 8051 port 2, bit 1 or TX of serial port 1 8051 port 3, bit 5 or pulse width modulator 3's output or Timer / Counter 1 external input 8051 port 3, bit 4 or pulse width modulator 2's output or Timer / Counter 0 external input 8051 port 3, bit 3 or interrupt 1 input configurable as level or edge sensitive Ground connection digital part 8051 port 0, bit 0 or SPI master interface serial clock output or Flash programming SPI slave clock input. 8051 port 0, bit 1 or SPI interface master output or Flash programming SPI slave serial data input 8051 port 1, bit 1 8051 port 1, bit 2 8051 port 1, bit 3 8051 port 1, bit 4 8051 port 2, bit 2 Digital power supply Ground connection digital part 8051 port 2, bit 3 Digital power supply 8051 port 2, bit 4 8051 port 2, bit 5 8051 port 3, bit 2 or interrupt 0 input configurable as level or edge sensitive 8051 port 3, bit 1 or TX of serial port 0 8051 port 3, bit 0 or RX of serial port 1 Digital ground connection Digital power supply 8051 port 0, bit 2 or SPI interface master input or Flash programming SPI slave serial data output 8051 port 0, bit 3 8051 port 1, bit 5 8051 port 1, bit 6
SCK (O) SCK (I) MO (O) SI (I) INT0 (I)
TXD0 (O) RXD0 (I) MI (I) SO (O) -
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 12 of 133
Chipcon
Pin # 55 56 57 58 59 60 61 62 63 64 Pin name P1.7 P2.6 P2.7
PROG RESET
SmartRF a CC1010
Pin type Digital high-Z I/O Digital high-Z I/O Digital high-Z I/O Digital input (pull-up) Description 8051 port 1, bit 7 8051 port 2, bit 6 8051 port 2, bit 7 Flash program enable pad, active low
Alternate function RSSI (O), IF (O) -
Digital input (pull-up) System reset pin, active low Power (D) Analog input Analog input Analog input/output Power (A) Digital power supply ADC input channel 0 ADC input channel 1 ADC input channel 2, RSSI (Receiver signal strength indicator) output, or IF output when using external demodulator Analog ground connection ADC
DVDD AD0 AD1 AD2 AGND
A = Analog, D = Digital, I = input, O= Output
Pin description
AVDD, DVDD Supply voltages for analog and digital modules respectively. All supply pins should be decoupled by capacitors. In particular, the digital and analog supply domains should be properly decoupled from each other. The placement and size of decoupling capacitors and supply filtering are critical with respect to LO leakage and sensitivity. Chipcon's reference layout designs should be used (available from Chipcon's website). See also page 122 for layout recommendations. AGND, DGND Ground for analog and digital modules respectively. Normally one common ground plane is recommended. If two separate analog and digital grounds are used they should be interconnected in one place, and one place only. RFIN This is the RF input, internally connected to the low noise amplifier (LNA). The signal source (antenna) should be matched to the input impedance. A DC ground is needed for LNA biasing. RFOUT This is the RF output, internally connected to the power amplifier (PA). The external load (antenna) should be matched to the output impedance (optimum load impedance). This pin must be DC coupled to AVDD for PA biasing (open drain output). L1, L2 Connection to internal voltage controlled oscillator (VCO). An inductor should be connected between these pins. The inductor value will determine the VCO tuning range. The inductor should be place very close to the pins in order to minimize paracitic inductance. CHP_OUT Charge Pump output. If the RF transceiver is configured for external loop filter this is the current output from the charge pump. Normally the internal loop filter should be used and this pin should be left open (not connected). RBIAS Current output from internal band gap cell bias generator. A precision resistor (82 k, 1%) should be connected between
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 13 of 133
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this pin and ground to set the correct bias current level. XOSC_Q1, XOSC_Q2 These are the main oscillator connection pins. An external crystal should be connected between these pins, and load capacitors should be connected between each pin and ground. If an external oscillator is used, the clock signal should be connected to the XOSC_Q1 pin, and XOSC_Q2 should be left open (not connected). XOSC32_Q1, XOSC32_Q2 These are the real time clock (RTC) oscillator connection pins. An external crystal should be connected between these pins, and load capacitors should be connected between each pin and ground. If an external oscillator is used, the clock signal should be connected to the XOSC32_Q1 pin, and XOSC32_Q2 should be left open (not connected). POR_E Enable signal for the on-chip power-on reset module. The power-on reset is enabled when POR_E is connected to DVDD and disabled when connected to DGND.
SmartRF a CC1010
AD2 (RSSI/IF) Analog input to A/D converter channel 2. This pin can also be configured to be RSSI output or IF output. The pin is configured by the FREND register. When not used this pin can be left open (not connected). PORT 0 Port 0 is a 4-bit (P0.3-P0.0) bi-directional CMOS I/O port with 2 mA drivers. A direction register (P0DIR) controls whether each pin is an output or input and the register P0 is used to read the input or control the logical value of the output. Pins P0.0 - P0.2 can be configured to become a master SPI interface in register SPCR and will then override P0(2:0), P0DIR(2) and P0DIR(1). Used as SPI interface, P0.0 is SCK, P0.1 is MOSI, and P0.2 is MISO. PORT 1 Port 1 is an 8-bit (P1.7-P1.0) bidirectional CMOS I/O port with 2 mA drivers. A direction register (P1DIR) controls whether each pin is an output or input and the register P1 is used to read the input or control the logical value of the output. PORT 2 Port 2 is an 8-bit (P2.7-P2.0) bidirectional CMOS I/O port with 2 mA drivers, except for P2.3 that has an 8 mA output buffer. A direction register (P2DIR) controls whether each pin is an output or input and the register P2 is used to read the input or control the logical value of the output. Pins P2.0 and P2.1 can be configured to become the RXD1 and TXD1 pin, respectively, of UART 1. PORT 3 Port 3 is a 6-bit (P3.5-P3.0) bi-directional CMOS I/O port with 2 mA drivers. A direction register (P3DIR) controls whether each pin is an output or input. The register
PROG
Active low Flash programming enable pin. When this signal is active (driven to DGND) a Flash programmer can be connected to the SPI interface. Under normal operation it must be driven to DVDD.
RESET
Active low asynchronous system reset. It has an internal pull-up resistor and can be left unconnected during normal operation. AD0, AD1 Analog inputs to A/D converter channels 0 and 1 respectively. When not used these pins can be left open (not connected).
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 14 of 133
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P3 is used to read the input or control the logical value of the output. Pins P3.0 and P3.1 can be configured to become the RXD0 and TXD0 pin, respectively, of UART 0. Pins P3.2 and P3.3 are connected to the external interrupt inputs INT0 and INT1, respectively, and can cause interrupts if the corresponding interrupt enable flags
SmartRF a CC1010
are set in register IE. The interrupts inputs can be configured to be either levelsensitive or edge-sensitive. Pins P3.4 and P3.5 can be configured to become the pulse width modulator (PWM) outputs of Timer/PWM 2 and Timer/PWM 3, respectively. When pulse width modulation is enabled the corresponding bits in P3DIR and P3 are overridden.
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 15 of 133
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Block Diagram
SmartRF a CC1010
The CC1010 Block Diagram is shown in Figure 2 below.
Programmable I/O (General purpose or alternate function) Port 0 POR_E RAM Arbiter Power-on reset Port 1 32 kB FLASH DES Module FLASH Programming DMA 2048 byte SRAM Port 2
Port 3
128 byte SRAM Watchdog Timer RESET PROG SPI Reset Generation
Timers/ PWMs 8051 core Interrupt Controller Timers/ Counters General purpose I/O UARTs UARTs Special Function Registers (SFRs) Realtime Clock 32 kHz crystal Clock Multiplexer
AD0 AD1 AD2 (RSSI/IF) MUX
ADC
System clock
RF Transceiver MIXER RF_IN LNA IF RSSI IF stage MODEM CODEC, Bit synchronizer, Serializer/Deserializer
:N.n
Bias Bias resistor
RF_OUT
PA
VCO
LPF
CHP
PD
:R
Main Crystal Oscillator 3-24 MHz crystal
L1
L2
CHP_OUT
VCO inductor
Figure 2. CC1010 Block Diagram
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 16 of 133
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8051 Core
General description The CC1010 microcontroller core is based on the industry-standard 8051 architecture. The MCU core is 8-bit, with program and data memory located in separate memory spaces (Harvard architecture). The internal registers are organised as four banks of 8 registers each. The instruction set supports direct, indirect and register addressing modes. Program memory can be addressed using indexed addressing. The core registers are comprised of an accumulator, a stack pointer and dual data pointer registers in addition to the general registers. Data memory is split into internal and external RAM. The name "external RAM" is in fact misleading since in the case of the CC1010 all the RAM is internal to the chip. The difference between external and internal is that external RAM can only be accessed by a few instructions. Therefore, frequently-accessed variables as well as the stack should be kept in internal RAM. Reset
SmartRF a CC1010
The various peripherals are controlled through Special Function Registers (SFRs) located in the internal RAM space. The 8051 core is instruction set compatible with the industry standard 8051. It also has one additional instruction, TRAP, to enable advanced in-circuitdebugging features. This is described on page 41. The instruction cycle time is 4 clock cycles, which typically gives an 2.5X average reduction in instruction execution time over the original Intel 8051. Peripheral units, including general purpose I/O, 2 standard 8051 timers, 2 extra timers with PWM functionality, a watchdog timer, a real-time clock, an SPI master interface, hardware DES encryption, a true random bit generator and ADC are all described from page 43 and out. Dual data pointers are available for faster data transfer.
CC1010 must be reset at start-up. There are several sources for reset in CC1010 :
* External reset pin, RESET . Applying a low signal to this pin at any time will reset almost all registers in CC1010. Exceptions can be found in Table 33 on page 126 The input is asynchronous and is synchronised internally, so that the reset can be released independent of the timing of the active clock signal. If the main crystal oscillator is inactive, the reset input should be held long enough for the oscillator to start up and stabilize. See Electrical Specifications page 7 for oscillator start-up timing. Power On Reset (POR). The internal POR module can generate reset upon power-up. Special requirements for power consumption or power supply
voltage may require an external POR module, as described in the Power On Reset (Brown-Out Detection) section at page 57. * Brown-out detection reset. The POR will also detect low supply voltage and generate a reset. Watchdog timer reset. The watchdog timer can generate a reset, as described in the section on page 56. ADC reset. The ADC module can be programmed to generate a reset signal if its inputs exceed a programmed threshold. See the ADC section on page 75 for details.
*
*
*
The POR and ADC reset signals will be held for 1024 clock periods after the signal is released. This will ensure a safe clock start-up if the crystal oscillator is currently not running.
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Memory Map The CC1010 memory map is shown in Figure 3.
SmartRF a CC1010
CC1010 has 2 blocks of RAM on chip. This includes the 128 bytes Internal RAM and the 2048 bytes External RAM. (The 2048byte RAM will be referred to as External RAM, although it is on-chip. Direct access to off-chip RAM is not implemented.)
Access to the internal RAM is performed using the MOV instruction. MOV A, @Ri, MOV @Ri, A and MOV @Ri, #data use indirect addressing. MOV A, direct, MOV Rn, direct, MOV direct, A, MOV direct, Rn, MOV direct, direct and MOV direct, #data use direct addressing. MOV @Ri, direct uses indirect and direct addressing. All direct addressing instructions can also be used to access the SFRs. CC1010 also implements the option to access SFRs indirectly, as described in the In Circuit Debugging section on page 41. CC1010 has dual data pointers to external RAM, provided in the 16 bit registers DPTR0 and DPTR1 (SFRs DPH0, DPL0, DPH1 and DPL1). If a high-level language compilator is used, it should be set up to make use of both pointers for better performance. The data pointer is selected through DPS.SEL. Access to the external RAM is performed using the MOVX instruction and indirect addressing using either the 16 bit data pointers or the 8 bit registers R0 or R1
MPAGE. together with MOVX A, @DPTR and MOVX @DPTR, A moves data to (from) the accumulator, from (to) the address pointed to by the currently selected data pointer.
The instructions MOVX A, @Ri and MOVX @Ri, A moves data to (from) the accumulator, from (to) the address given by the memory page address register MPAGE and the register Ri (R0 or R1). MPAGE gives the 8 most significant address bits, while the register Ri gives the 8 least significant bits. In many 8051 implementations, this type of external RAM access is performed using P2 to give the most significant address bits. Existing software may therefore have to be adapted to make use of MPAGE instead of P2. The program memory can be read using the MOVC A, @A+DPTR and MOVC A, @A+PC instructions, which moves a byte from the program memory address given by A+DPTR or A+PC respectively. The program memory can not be written using MOV commands, but uses the method described in the 8051 Flash Programming section on page 39.
CC1010 also provides a possibility to stretch the access cycle to external RAM, through CKCON.MD(2:0) (see page 51). The default value for CKCON.MD is "001". It is recommended to set CKCON.MD to "000" for faster RAM access.
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SmartRF a CC1010
Flash Program Memory 0x7FFF External RAM 0x7FF
Internal RAM / SFR 0xFF Special Function Registers (SFR), accessible through Direct Addressing 0x7F Internal RAM Accessible through Direct and Indirect Addressing 0x00 0x00 0x00 Accesible through indirect addressing Accesible through indirect addressing
Figure 3. Memory Map DPL0 (0x82) - Data Pointer 0, low byte
Bit 7:0 Name
DPL0(7:0)
R/W R/W
Description Data Pointer 0, low byte
DPH0 (0x83) - Data Pointer 0, high byte
Bit 0 Name
DPH0(7:0)
R/W R/W
Description Data Pointer 0, high byte
DPL1 (0x84) - Data Pointer 1, low byte
Bit 7:0 Name
DPL1(7:0)
R/W R/W
Description Data Pointer 1, low byte
DPH1 (0x85) - Data Pointer 1, high byte
Bit 7:0 Name
DPH1(7:0)
R/W R/W
Description Data Pointer 1, high byte
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DPS (0x86) - Data Pointer Select
Bit 7:1 0 Name
SmartRF a CC1010
SEL
R/W R0 R/W
Description Reserved, read as 0 Data Pointer Select for external RAM access 0 : DPH0 and DPL0 are used 1 : DPH1 and DPL1 are used
MPAGE (0x92) - Memory Page Select Register
Bit 7:0 Name
MPAGE(7:0)
R/W R/W
Description Memory Page
A total of 119 Special Function Registers (SFRs) are accessible from the microcontroller core. The names and addresses of all SFRs are listed in Table 5. All standard 8051 registers are available, in addition to SFRs which are CC1010 specific, controlling modules such as the RF Transceiver, DES encryption, ADC and Real-Time Clock. Table 5. CC1010 SFR Overview
0/8 0xF8 0xF0 0xE8 0xE0 0xD8 0xD0 0xC8 0xC0 0xB8 0xB0 0xA8 0xA0 0x98 0x90 0x88 0x80
EIP B EIE ACC EICON PSW RFMAIN SCON1 IP P3 IE P2 SCON0 P1 TCON P0
All SFRs will be described in the following sections. A more detailed overview is provided in Table 33 on page 126, which also includes all reset values. SFRs with addresses ending with 0 or 8 (leftmost column of Table 5) are bit adressable.
1/9
TEST0 FSHAPE7 FSDELAY CURRENT MODEM2 X32CON RFBUF SBUF1 RDATA TCON2 SPCR SBUF0 EXIF TMOD SP
2/A
TEST1 FSHAPE6 FSEP0 PA_POW MODEM1 WDT FREQ_0A RFCON RADRL T2PRE SPDR MPAGE TL0 DPL0
3/B
TEST2 FSHAPE5 FSEP1 PLL MODEM0 PDET FREQ_1A CRPCON RADRH T3PRE SPSR ADCON TL1 DPH0
4/C
TEST3 FSHAPE4 FSCTRL LOCK MATCH BSYNC FREQ_2A CRPKEY CRPINI4 CRPINI0 T2 P0DIR ADDATL TH0 DPL1
5/D
TEST4 FSHAPE3 RTCON CAL FLTIM FREQ_0B CRPDAT CRPINI5 CRPINI1 T3 P1DIR ADDATH TH1 DPH1
6/E
TEST5 FSHAPE2 FREND PRESCALER FREQ_1B CRPCNT CRPINI6 CRPINI2 FLADR P2DIR ADCON2 CKCON DPS
7/F
TEST6 FSHAPE1 TESTMUX RESERVED FREQ_2B RANCON CRPINI7 CRPINI3 FLCON P3DIR CHVER ADTRH PCON
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CPU Registers
SmartRF a CC1010
CC1010 provides 4 register banks of 8 registers each. These register banks are mapped in the the internal data memory (see the Memory section on page 31) at addresses 0x00 - 0x07, 0x08 - 0x0F, 0x10 - 0x17 and 0x18 - 0x1F. Each register bank contains the 8 8-bit registers R0 through R7. The different register banks are selected through the Program Status Word PSW.RS(1:0) as shown below. PSW also contains carry, overflow and
PSW (0xD0) - Program Status Word
Bit 7 Name
parity flags that reflect the current CPU state. In addition, the CPU uses the accumulator register A (accessed via the SFR space as ACC), B (for multiplication and division) and the stack pointer SP. These registers are shown below. Note that the hardware stack pointer SP is increased when pushing and decreased when popping data, unlike many other microcontroller architectures.
CY
R/W R/W
6
AC
R/W
5 4 3
F0 RS1 RS0
R/W R/W R/W
2 1 0
OV F1 P
R/W R/W R/W
Description Carry Flag, set to 1 when the last arithmetic operation resulted in a carry (during addition) or borrow (during subtraction), otherwise cleared to 0 by all arithmetic operations. CY is also used for rotation instructions. Auxiliary carry flag. Set to 1 when the last arithmetic operation resulted in a carry into (during addition) or borrow from (during subtraction) the high order nibble, otherwise cleared to 0 by all arithmetic operations. Flag 0 (Available to the user for general purpose) Register bank select. RS1 RS0 Working register bank and address 0 0 Bank0 0x00-0x07 0 1 Bank1 0x08-0x0F 1 0 Bank2 0x10-0x17 1 1 Bank3 0x18-0x1F Overflow flag. Set to 1 when the last arithmetic operation resulted in a carry (addition), borrow (subtraction), or overflow (multiply or divide). Otherwise, the bit cleared to 0 by all arithmetic operations. Flag 1 (Available to the user for general purpose) Parity flag. Set to 1 when the modulo-2 sum of the 8 bits in the accumulator is 1 (odd parity), cleared to 0 on even parity.
ACC (0xE0) - Accumulator Register
Bit 7:0 Name
ACC(7:0)
R/W R/W
Description Accumulator
B (0xF0) - B Register
Bit 7:0 Name
B(7:0)
R/W R/W
Description B is used for multiplication and division
SP (0x81) - Stack Pointer
Bit 7:0 Name
SP(7:0)
R/W R/W
Description Stack Pointer, used for pushing and poping data to and from the stack. Note that the reset value for SP is 0x07
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Instruction Set Summary The 8051 instruction set is summarised in Table 6 below. All mnemonics are copyright a Intel Corporation 1980. One non-standard 8051 instruction, TRAP, with opcode 0xA5 is included to enable setting of breakpoints. This instruction is described in the In Circuit Debugging section at page 41. Symbols used in the table are: * * * * * * * * * A - Accumulator AB - Register pair A and B B - Multiplication register C - Carry flag DPTR - Data pointer Rn - Register R0 - R7 PC - Program counter direct - 8-bit data address (Internal RAM 0x00 - 0x7F, SFRs 0x80-0xFF) @Ri - Internal register pointed to by R0 or R1 (except MOVX)
SmartRF a CC1010
* * * * * *
rel - Two's complement offset byte used by SJMP and conditional jumps bit - Direct bit address #data - 8-bit constant #data 16 - 16-bit constant addr 16 - 16-bit destination address addr 11 - 11-bit destination address, used by ACALL and AJMP. The branch will be within the same 2 kB block of program memory of the first byte of the following instruction.
The `Bytes' column shows the number of bytes of Flash memory used. Further, the number of instruction cycles is shown. Each instruction cycle require four clock cycles. The 4 rightmost columns shows which flags in the program status word PSW (see page 21) are affected by the instructions.
Table 6. Instruction Set Summary
Mnemonic Description Instr. Cycles Hex Opcode
Bytes
OV x x x x x x x x x x x x
AC
CY
ADD A, Rn ADD A, direct ADD A, @Ri ADD A, #data ADDC A, Rn ADDC A, direct ADDC A, @Ri ADDC A, #data SUBB A, Rn SUBB A, direct SUBB A, @Ri SUBB A, #data
Add register to A Add direct byte to A Add data memory to A Add immediate to A Add register to A with carry Add direct byte to A with carry Add data memory to A with carry Add immediate to A with carry Subtract register from A with borrow Subtract direct byte from A with borrow Subtract data memory from A with borrow Subtract immediate from A with borrow
1 2 1 2 1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2 1 2 1 2
28-2F 25 26-27 24 38-3F 35 36-37 34 98-9F 95 96-97 94
x x x x x x x x x x x x
x x x x x x x x x x x x
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Mnemonic Description
SmartRF a CC1010
Instr. Cycles Hex Opcode
Bytes
OV x x
AC
CY
INC A INC Rn INC direct INC @Ri DEC A DEC Rn DEC direct DEC @Ri INC DPTR MUL AB DIV AB DA A ANL ANL ANL ANL ANL ANL ORL ORL ORL ORL ORL ORL XRL XRL XRL XRL XRL XRL A, Rn A, direct A, @Ri A, #data direct, A direct, #data A, Rn A, direct A, @Ri A, #data direct, A direct, #data A, Rn A, direct A, @Ri A, #data direct, A direct, #data
CLR A CPL A SWAP A RL A RLC A RR A RRC A MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A
Increment A Increment register Increment direct byte Increment data memory Decrement A Decrement register Decrement direct byte Decrement data memory Increment data pointer Multiply A by B Divide A by B Decimal adjust A Logical AND register to A AND direct byte to A AND data memory to A AND immediate to A AND A to direct byte AND immediate data to direct byte OR register to A OR direct byte to A OR data memory to A OR immediate to A OR A to direct byte OR immediate data to direct byte Exclusive-OR register to A Exclusive-OR direct byte to A Exclusive-OR data memory to A Exclusive-OR immediate to A Exclusive-OR A to direct byte Exclusive-OR immediate to direct byte Clear A Complement A Swap nibbles of A Rotate A left Rotate A left through carry Rotate A right Rotate A right through carry Data Transfer Move register to A Move direct byte to A Move data memory to A Move immediate to A Move A to register
1 1 2 1 1 1 2 1 1 1 1 1 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 1 2 1 2 1
1 1 2 1 1 1 2 1 3 5 5 1 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 1 2 1 2 1
04 08-0F 05 06-07 14 18-1F 15 16-17 A3 A4 84 D4 58-5F 55 56-57 54 52 53 48-4F 45 46-47 44 42 43 68-6F 65 66-67 64 62 63 E4 F4 C4 23 33 03 13 E8EF E5 E6E7 74 F8-FF
x x x
x x
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Mnemonic Description
SmartRF a CC1010
Instr. Cycles Hex Opcode
Bytes
OV
AC
CY
MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct MOV direct, @Ri MOV direct, #data MOV @Ri, A MOV @Ri, direct MOV @Ri, #data MOV DPTR, #data MOVC A, @A+DPTR MOVC A, @A+PC MOVX A, @Ri MOVX A, @DPTR MOVX @Ri, A MOVX @DPTR, A PUSH direct POP direct XCH A, Rn XCH A, direct XCH A, @Ri XCHD A, @Ri CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C, bit ANL C, /bit ORL C, bit ORL C, /bit MOV C, bit MOV bit, C ACALL addr 11 LCALL addr 16 RET
Move direct byte to register Move immediate to register Move A to direct byte Move register to direct byte Move direct byte to direct byte Move data memory to direct byte Move immediate to direct byte MOV A to data memory Move direct byte to data memory Move immediate to data memory Move immediate to data pointer Move code byte relative DPTR to A Move code byte relative PC to A Move external data (A8) to A Move external data (A16) to A Move A to external data (A8) Move A to external data (A16) Push direct byte onto stack Pop direct byte from stack Exchange A and register Exchange A and direct byte Exchange A and data memory Exchange A and data memory nibble Boolean Clear carry Clear direct bit Set carry Set direct bit Complement carry Complement direct bit AND direct bit to carry AND direct bit inverse to carry OR direct bit to carry OR direct bit inverse to carry Move direct bit to carry Move carry to direct bit Branching Absolute call to subroutine Long call to subroutine Return from subroutine
2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 1 2 1 2 1 2 2 2 2 2 2 2 2 3 1
2 2 2 2 3 2 3 1 2 2 3 3 3 2-9 2-9 2-9 2-9 2 2 1 2 1 1 1 2 1 2 1 2 2 2 2 2 2 2 3 4 4
A8AF 78-7F F5 88-8F 85 86-87 75 F6-F7 A6A7 76-77 90 93 83 E2E3 E0 F2-F3 F0 C0 D0 C8CF C5 C6C7 D6D7 C3 C2 D3 D2 B3 B2 82 B0 72 A0 A2 92 11-F1 12 22 x x x x x x x x
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Mnemonic Description
SmartRF a CC1010
Instr. Cycles Hex Opcode
Bytes
OV
AC
CY
RETI AJMP addr 11 LJMP addr 16 SJMP rel JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel JMP @A+DPTR JZ rel JNZ rel CJNE A, direct, rel CJNE A, #d, rel CJNE Rn, #d, rel CJNE @Ri, #d, rel DJNZ Rn, rel DJNZ direct, rel NOP TRAP
Return from interrupt Absolute jump unconditional Long jump unconditional Short jump (relative address) Jump on carry = 1 Jump on carry = 0 Jump on direct bit = 1 Jump on direct bit = 0 Jump on direct bit = 1 and clear Jump indirect relative DPTR Jump on accumulator = 0 Jump on accumulator /= 0 Compare A and direct, jump relative if not equal Compare A and immediate, jump relative if not equal Compare reg and immediate, jump relative if not equal Compare ind and immediate, jump relative if not equal Decrement register, jump relative if not zero Decrement direct byte, jump relative if not zero Misc No operation Set EICON.FDIF = 1, used for breakpoints
1 2 3 2 2 2 3 3 3 1 2 2 3 3 3 3 2 3 1 1
4 3 4 3 3 3 4 4 4 3 3 3 4 4 4 4 3 4 1 3
32 01-E1 02 80 40 50 20 30 10 73 60 70 B5 B4 B8BF B6B7 D8DF D5 00 A5
x x x x
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Interrupts In CC1010 there are a total of 15 interrupt sources, which share 12 interrupt lines. These are all shown in Table 7. Each interrupt's natural priority, interrupt vector, Table 7. CC1010 Interrupt overview
Interrupt Flash / Debug interrupt External Interrupt 0 Timer 0 Interrupt External Interrupt 1 Timer 1 Interrupt Serial Port 0 Transmit Interrupt Serial Port 0 Receive Interrupt Serial Port 1 Transmit Interrupt Serial Port 1 Receive Interrupt RF Transmit / Receive Interrupt Timer 2 Interrupt ADC Interrupt Natural Priority 0 1 2 3 4 5 6 7 8 9 Priority Control
SmartRF a CC1010
interrupt enable and interrupt flag, which is also shown in the table, will be described below.
IP.PX0 IP.PT0 IP.PX1 IP.PT1 IP.PS0 IP.PS1 EIP.PRF EIP.PT2 EIP.PAD
Interrupt Vector 0x33 0x03 0x0B 0x13 0x1B 0x23 0x3B 0x43 0x4B 0x53
Interrupt Enable
Interrupt Flag
EICON. FDIE IE.EX0 IE.ET0 IE.EX1 IE.ET1 IE.ES0 IE.ES1 EIE.RFIE EIE.ET2 EIE.ADIE and ADCON2. ADCIE EIE.ADIE
and
EICON. FDIF TCON.IE0 (*) TCON.TF0 (*) TCON.IE1 (*) TCON.TF1 (*) SCON0.TI_0 SCON0.RI_0 SCON1.TI_1 SCON1.TI_1 EXIF.RFIF EXIF.TF2 EXIF.ADIF
and
DES Encryption / Decryption Interrupt
ADCON2. ADCIF EXIF.ADIF
and
Timer 3 Interrupt Realtime Clock Interrupt
EIP.PT3 EIP.PRTC (*) - Interrupt flag is cleared by hardware.
Interrupt Masking
10 11
0x5B 0x63
CRPCON. CRPIE EIE.ET3 EIE.RTCIE
CRPCON. CRPIF EXIF.TF3 EICON.RTCIF
IE.EA is the global interrupt enable for all interrupts, except the Flash / Debug interrupt. When IE.EA is set, each interrupt is masked by the interrupt enable bits listed in Table 7. When IE.EA is cleared, all interrupts are masked, except the Flash / Debug interrupt, which has its own interrupt mask bit, EICON.FDIE.
Interrupt Processing When an enabled interrupt occurs, the CPU jumps to the address of the interrupt service routine (ISR) associated with that interrupt, as shown in Table 7. Most interrupts can also be initiated by setting the associated interrupt flag from software.
CC1010 executes the ISR to completion unless another interrupt set at an higher interrupt level occurs. Each ISR ends with a RETI (return from interrupt) instruction. After executing the RETI, CC1010 returns to the next instruction that would have been executed if the interrupt had not occurred. CC1010 always completes the instruction in progress before servicing an interrupt. If the instruction in progress is RETI, or a write access to any of the IP, IE, EIP, or EIE SFRs, CC1010 completes one additional instruction before servicing the interrupt.
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IE (0xA8) - Interrupt Enable Register
Bit 7 6 Name
SmartRF a CC1010
EA ES1
R/W R/W R/W
5 4
ES0
R/W R/W
3
ET1
R/W
2
EX1
R/W
1
ET0
R/W
0
EX0
R/W
Description Global Interrupt enable / disable 0 : All interrupts except the Flash / debug interrupt are disabled 1 : Each interrupt is enabled by its individual masking bit Serial Port 1 interrupt enable / disable 0 : Interrupt is disabled 1 : Interrupt is enabled, when also EA is set Reserved for future use Serial Port 0 interrupt enable / disable 0 : Interrupt is disabled 1 : Interrupt is enabled, when also EA is set Timer 1 interrupt enable / disable 0 : Interrupt is disabled 1 : Interrupt is enabled, when also EA is set External interrupt 1 (from P3.3) enable / disable 0 : Interrupt is disabled 1 : Interrupt is enabled, when also EA is set Timer 0 interrupt enable / disable 0 : Interrupt is disabled 1 : Interrupt is enabled, when also EA is set External interrupt 0 (from P3.2) enable / disable 0 : Interrupt is disabled 1 : Interrupt is enabled, when also EA is set
EIE (0xE8) - Extended Interrupt Enable Register
Bit 7 6 5 4 Name
RTCIE
R/W R1 R1 R1 R/W
3
ET3
R/W
2
ADIE
R/W
1
ET2
R/W
0
RFIE
R/W
Description Reserved, read as 1 Reserved, read as 1 Reserved, read as 1 Realtime Clock interrupt enable / disable 0 : Interrupt is disabled 1 : Interrupt is enabled, when also EA is set Timer 3 interrupt enable / disable 0 : Interrupt is disabled 1 : Interrupt is enabled, when also EA is set ADC / DES interrupt enable / disable 0 : Interrupt is disabled 1 : Interrupt is enabled, when also EA is set Timer 2 interrupt enable / disable 0 : Interrupt is disabled 1 : Interrupt is enabled, when also EA is set RF Interrupt enable / disable 0 : Interrupt is disabled 1 : Interrupt is enabled, when also EA is set
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EICON (0xD8) - Extended Interrupt Control
Bit 7 6 5 Name
SmartRF a CC1010
SMOD1 FDIE
R/W R/W R1 R/W
4
FDIF
R/W
3
RTCIF
R/W
2 1 0
-
R0 R0 R0
Description Serial Port 1 baud rate doubler enable / disable 0 : Serial Port 1 baud rate is normal 1 : Serial Port 1 baud rate is doubled Reserved, read as 1 Flash / Debug interrupt enable 0 : Interrupt is disabled 1 : Interrupt is enabled (independent of IE.EA) Flash / Debug interrupt flag FDIF is set by hardware when an 8051-initiated write to Flash program memory is completed or a TRAP instruction is executed. FDIF may also be set by software. FDIF must be cleared by software before exiting the ISR. Realtime clock interrupt flag RTCIF is set by hardware when an interrupt request is generated from the realtime clock. RTCIF may also be set by software. RTCIF must be cleared by software before exiting the ISR. Reserved, read as 0 Reserved, read as 0 Reserved, read as 0
EXIF (0x91) - Extended Interrupt Flag
Bit 7 Name
TF3
R/W R/W
6
ADIF
R/W
5
TF2
R/W
4
RFIF
R/W
3 2 1 0
-
R1 R0 R0 R0
Description Timer 3 interrupt flag. TF3 is set by hardware when an interrupt request is generated from Timer 3. TF3 may also be set by software. TF3 must be cleared by software before exiting the ISR. ADC / DES Interrupt flag. ADIF is set by hardware when an interrupt request is generated from the ADC block (ADCON2.ADCIF) or by the DES Encryption / Decryption block (CRPCON.CRPIF). These interrupts must also be enabled by setting ADCON2.ADCIE and CRPCON.CRPIE. ADIF may also be set by software. ADIF must be cleared by software before exiting the ISR Timer 2 interrupt flag. TF2 is set by hardware when an interrupt request is generated from Timer 2. TF2 may also be set by software. TF2 must be cleared by software before exiting the ISR RF Transmit / receive interrupt flag. RFIF is set by hardware when an interrupt request is generated from the RF transceiver block. RFIF may also be set by software. RFIF must be cleared by software before exiting the ISR. Reserved, read as 1 Reserved, read as 0 Reserved, read as 0 Reserved, read as 0
Interrupt Priority Interrupts are prioritised in two stages: Interrupt level and natural priority. The
interrupt level (low, high or highest) takes precedence over the natural priority. The Flash / Debug Interrupt, if enabled, always has the highest priority and is the
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only interrupt that can have the highest priority. All other interrupts can be assigned either low or high priority, set by the registers IP and EIP listed below. Two interrupts with the same interrupt priority that occur simultaneously are resolved through their natural priority. The IP (0xB8) - Interrupt Priority Register
Bit 7 6 5 4 3 2 Name
SmartRF a CC1010
natural priority is shown in Table 7. The interrupt having the lowest natural priority will be serviced first. Once an interrupt is being serviced, only an interrupt of higher priority level can interrupt the service routine of the interrupt currently being serviced.
PS1 PS0 PT1 PX1
R/W R1 R/W R/W R/W R/W R/W
1 0
PT0 PX0
R/W R/W
Description Reserved, read as 1 Serial Port 1 interrupt priority control 0 : Interrupt has low priority 1 : Interrupt has high priority Reserved for future use Serial Port 0 interrupt priority control 0 : Interrupt has low priority 1 : Interrupt has high priority Timer 1 interrupt priority control 0 : Interrupt has low priority 1 : Interrupt has high priority External Interrupt 1 (from P3.3) interrupt priority control 0 : Interrupt has low priority 1 : Interrupt has high priority Timer 0 interrupt priority control 0 : Interrupt has low priority 1 : Interrupt has high priority External Interrupt 0 (from P3.2) interrupt priority control 0 : Interrupt has low priority 1 : Interrupt has high priority
EIP (0xF8) - Extended Interrupt Priority Register
Bit 7 6 5 4 3 2 1 0 Name
PRTC PT3 PAD PT2 PRF
R/W R1 R1 R1 R/W R/W R/W R/W R/W
Description Reserved, read as 1 Reserved, read as 1 Reserved, read as 1 Realtime Clock interrupt priority control 0 : Interrupt has low priority 1 : Interrupt has high priority Timer 3 interrupt priority control 0 : Interrupt has low priority 1 : Interrupt has high priority ADC / DES interrupt priority control 0 : Interrupt has low priority 1 : Interrupt has high priority Timer 2 interrupt priority control 0 : Interrupt has low priority 1 : Interrupt has high priority 0 : Interrupt has low priority 1 : Interrupt has high priority
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Main Crystal Oscillator An external clock signal or the main crystal oscillator can be used as main frequency reference and microcontroller clock signal. An external clock signal should be connected to XOSC_Q1, while XOSC_Q2 should be left open. The microcontroller core and main oscillator will operate at any frequency in the range 3 - 24 MHz. However, the crystal frequency should be in the range 34, 6-8 or 9-24 MHz because the crystal frequency is used as reference for the data rate in the RF transceiver part (as well as other internal functions). The following frequencies are recommended as they will provide "standard" data rates: 3.6864, 7.3728, 11.0592, 14.7456, 18.4320 and 22.1184 MHz. The selected crystal frequency range must be set in MODEM0.XOSC_FREQ(2:0) in order to get the correct data rate (see page 88). Using the main crystal oscillator, the crystal must be connected between the pins XOSC_Q1 and XOSC_Q2. The oscillator is designed for parallel mode operation of the crystal. In addition loading capacitors (C171 and C181) for the crystal are required. The loading capacitor values depend on the total load capacitance, CL, specified for the crystal. The total load capacitance seen between the crystal
SmartRF a CC1010
terminals should equal CL for the crystal to oscillate at the specified frequency.
CL =
1 1 1 + C171 C181
+ C parasitic
The parasitic capacitance is constituted by pin input capacitance and PCB stray capacitance. Typically the total parasitic capacitance is 3-5pF. A trimming capacitor may be placed across C171 for initial tuning if necessary. The main crystal oscillator circuit is shown in Figure 4. Typical component values for different values of CL are given in Table 8. Recommended load capacitance versus frequency is given in Table 4 at page 7. The initial tolerance, temperature drift, ageing and load pulling should be carefully specified in order to meet the required frequency accuracy in a certain application. By specifying the total expected frequency accuracy in SmartRF Studio together with data rate and frequency separation, the software will calculate the total bandwidth and compare to the available IF bandwidth. Any contradictions will be reported by the software and a more accurate crystal will be recommended if required.
XOSC_Q1 XTAL C181 C171
XOSC_Q2
Figure 4. Crystal oscillator circuit
Table 8. Crystal oscillator component values
Item C171 C181 CL= 12 pF 15 pF 15 pF CL= 22 pF 33 pF 33 pF
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Power and Clock Modes Several power modes are defined to save power when running CC1010. The modes are described below. See also Table 9. Active Mode In active mode the 8051 is running normally, executing instructions from the Flash program memory. The clock used in this mode could either be the main crystal oscillator, or it could be the 32 kHz Realtime clock (RTC). The current consumption depends on the actual frequency used. Idle Mode After completing the instruction that sets the PCON.IDLE bit, Idle Mode is entered. In Idle Mode, the 8051 processing is stopped and internal registers maintain their current data, but all peripherals are still running. There are 3 ways to exit Idle Mode: * Activate any enabled interrupt. This clears the IDLE bit, terminating Idle Mode, and executes the ISR associated with the received interrupt. The RETI instruction at the end of the ISR causes the 8051 to return to the instruction following the one that enabled Idle Mode. Activate any reset condition. All registers are then reset, and program execution will resume from address
Core Main osc. Active RTC osc. (32 kHz) Stopped Stopped Stopped Peripherals Main osc. RTC osc. (32 kHz) Main osc. RTC osc. (32 kHz) Stopped
SmartRF a CC1010
0x0000 when the reset condition is cleared. * Turn the power off and on. The Power On Reset module should then be enabled, or an external reset signal should be applied during power up.
Power-Down Mode After completing the instruction that sets the PCON.STOP bit, the controller core and the peripherals are stopped. In PowerDown Mode, the clock trees of the 8051 and peripherals are disabled. Only the ADC clock tree is running. This enables the ADC to generate reset as will be described in the ADC section. There are 2 ways to exit Power Down Mode: * Activate any reset condition. All registers are then reset, and program execution will resume when the reset condition is cleared. Program execution will then resume from address 0x0000. Turn the power off and on. The Power On Reset module should then be enabled, or an external reset signal should be applied during power up.
*
*
Table 9. Operating modes summary
Mode Typical current 1 consumption 10 mA at 11 MHz 1.1 mA 8.5 mA at 11 MHz 26 uA 0.2 uA Exit condition Writing SFR Writing SFR Interrupt Reset Power off/on Reset Power off/on
Idle Power-Down
Note 1: Flash duty-cycle reduction is used for all modes
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SmartRF a CC1010
Clock Modes The 8051 and its peripherals can be run on both the main crystal oscillator (Clock Mode 0) and the 32.768 kHz oscillator (Clock Mode 1). The clock mode is set in X32CON.CMODE. Entering Clock Mode 1 from Clock Mode 0 After reset, the 8051 and its peripherals are running on the main crystal oscillator, and the 32.768 kHz oscillator is in power down. To enter Clock Mode 1, the 32.768 kHz oscillator must first be powered up. This requires clearing X32CON.X32_PD and then waiting at least 160 ms, after which X32CON.CMODE can be set to enter Clock Mode 1. If an external 32.768 kHz clock source is already available in the system, this clock can be applied to the XOSC32_Q1 pin after setting the X32CON.X32_BYPASS bit. After 2 to 3 clock periods on the 32.768 kHz oscillator, a glitch free transition has been made from the main crystal oscillator to the 32.768 kHz oscillator. If desired, the main crystal oscillator can then be set in power down to save more power by setting RFMAIN.CORE_PD and RFMAIN.BIAS_PD. This has the disadvantage that a later transition from Clock Mode 1 to Clock Mode 0 will require PCON (0x87) - Power Control Register
Bit 7 6 5 4 3 2 1 0 Name
the main crystal oscillator to be powered up again, Since the Flash program memory draws a static current, Idle Mode together with Flash Power Control (see page 40) should be applied for maximum power saving in Clock Mode 1. RF communications cannot be performed in Clock Mode 1, since the 8051 and peripherals are running on the 32 kHz clock. Entering Clock Mode 0 from Clock Mode 1 To enter Clock Mode 0 from Clock Mode 1, the main crystal oscillator must first be set in power up (if powered down). This requires clearing RFMAIN.CORE_PD and RFMAIN.BIAS_PD and then waiting at least 5 ms (depend on main oscillator frequency, see Electrical Specifications page 7). If the oscillator is already powered up, no waiting is required. Clearing X32CON.CMODE will then cause a glitch free transition from Clock Mode 1 to Clock Mode 0 after 2 to 3 clock periods on the main crystal oscillator. Flash Power Control The Flash program memory current consumption can be controlled as described in the Flash Power Control section on page 40.
SMOD0 GF1 GF0 STOP IDLE
R/W R/W R/W R1 R1 R/W R/W R/W R/W
Description Serial Port 0 baud rate doubler enable. 0 : Serial Port 0 baud rate is not doubled 1 : Serial Port 0 baud rate is doubled Reserved Reserved, read as 1 Reserved, read as 1 General purpose flag 1. Bit-addressable, general purpose flag for software control. General purpose flag 0. Bit-addressable, general purpose flag for software control. Power Down (Stop) mode select. Setting the STOP bit places CC1010 core and peripherals in Stop Mode. Idle mode select. Setting the IDLE bit places CC1010 in Idle Mode (core is stopped but peripherals are running).
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SmartRF a CC1010
X32CON (0xD1) - 32.768 kHz Crystal Oscillator Control Register
Bit 7 6 5 4 3 2 Name
X32_BYPASS
R/W R0 R0 R0 R0 R0 R/W
1 0
X32_PD CMODE
R/W R/W
Description Reserved, read as 0 Reserved, read as 0 Reserved, read as 0 Reserved, read as 0 Reserved, read as 0 32.768 kHz oscillator bypass control signal 0 : The internal 32.768 kHz oscillator is used to generate the 32.768kHz clock 1 : The internal 32.768 kHz oscillator is bypassed, and an external clock signal can be applied to the XOSC32_Q1 pin. 32.768 kHz oscillator power down signal 0 : The oscillator is powered up (default after reset) 1 : The oscillator is powered down Select different Clock Modes for the 8051 and its peripherals. 0 : Clock Mode 0 is selected (default after reset) 1 : Clock Mode 1 is selected
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Flash Program Memory
SmartRF a CC1010
CC1010 has 32 kBytes of on-chip Flash program memory. It is divided into 256 pages of 128 bytes each. It can be programmed / erased through a serial SPI interface or page-by-page from the 8051 as described in the following sections.
The endurance for the Flash program memory is typically 20.000 erase / write cycles. The Flash program memory can be locked for further reading / writing by setting appropriate lock bits through the serial interface. Chip erase must be performed SPI Flash Programming The on chip Flash program memory can be programmed using the SPI Flash programming protocol described in this section. SPI Flash programming is enabled when the pin PROG is held low. This enables the SPI slave, using the pins SCK (P0.0) as the clock input, SI (P0.1) as the serial data input and SO (P0.2) as the serial data output.
to unlock the memory. This provides a way to prevent software from being copied by others. It can also prevent parts of the Flash memory from being modified by software, such as a boot loader which should remain unchanged. Other parts of the Flash may still be updated by the boot loader. For the security of the Flash protection, please refer to the disclaimer at the end of this document.
A Windows based Flash programmer is also available free of charge at the Chipcon web site. SPI Flash Programming Instructions 9 instructions are defined to perform the serial Flash programming. These are shown in Table 10.
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Table 10. SPI Flash Programming Instructions
Instruction Programming Enable Set Flash Timing Chip Erase Byte 1
1010 1100
SmartRF a CC1010
Byte 2
0101 0011
Byte 3
xxxx xxxx
Byte 4
xxxx xxxx
Operation
Enable serial programming after
PROG is set low
1010 1100
0101 1101
xxxx xxxx
xxii iiii
Set the Flash timing register Chip erase. Clears all pages, including the lock bits. Load data i to Programming Buffer at address b:H Write the loaded page at address a. Read data o at address a:b:H Write Lock Bits. Bits written will be ANDed together with the existing lock bits. Read lock bits. Read signature byte o at address s
1010 1100
100x xxxx
xxxx xxxx
xxxx xxxx
Load Program Memory Page Write Program Memory Page Read Program Memory
0100 H000
xxxx xxxx
bbbb bbxx
iiii iiii
0100 1100
aaaa aaaa
xxxx xxxx
xxxx xxxx
0010 H000
aaaa aaaa
bbbb bbxx
oooo oooo
Write Lock Bits Read Lock Bits Read Signature Byte
1010 1100
111x xxxx
xxxx xxxx
iiii iiii
0101 1000 0011 0000
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xsss
oooo oooo oooo oooo
a: Page address b: Even byte address H: Odd or even (high or low) byte c: Clock timing bits
s: Signature byte address i: Input data o: Output data x: Don't care
Each instruction is sent in the order bytes 1 to 4, most significant bits first. All 4 bytes must be sent, even if the last bits are 'x'.
The timing for the SPI interface is shown in Figure 5. All timing parameters are listed in Table 11.
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Tsck, high Tsck, low
SmartRF a CC1010
Tsck, rise Tsck, fall
SCK (P0.0) SI (P0.1) SO (P0.2) 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0
Tsi, setup
Tsi, hold
Tso, delay
Figure 5. SPI Flash Programming Timing Table 11. SPI Flash Programming Timing Parameters
Symbol Fsck Tsck, high Tsck, low Tsck, rise Tsck, fall Tsi, setup
Tsi, hold Tso, delay
Min 4 TXOSC 4 TXOSC TXOSC
TXOSC -
Max fXOSC / 8 TXOSC /2 TXOSC /2 TXOSC
Units
Conditions
The minimum time SCK must be held high The minimum time SCK must be held low The maximum rise time on SCK The maximum fall time on SCK The minimum setup time for SI before the positive edge on SCK The minimum hold time for SI after the positive edge on
ns ns
SCK
The delay from the negative edge on SCK to valid data on SO
Programming Enable Programming Enable is always the first instruction to be sent. It must be sent to synchronise the data flow and enable CC1010 to receive further instructions. Synchronisation is achieved when byte 2 of the instruction (0x53) is echoed back from the SPI interface as byte 3. If synchronisation is not achieved, byte 3 will return all zeros. In this case, an extra clock pulse should be inserted on SCK, and the Programming Enable instruction should be resent. If synchronisation is not successful within 32 attempts, Programming Enable is unsuccessful and further debugging is needed. Set Flash Timing The Set Flash Timing instruction is needed to generate internal timing for the Flash
module. FLTIM must be set in instruction byte 4 so that:
f XOSC f FLTIM XOSC 0.8MHz 0.4 MHz
It is recommended to set FLTIM to the smallest number satisfying the equation above, to reduce the time needed for Flash programming. For a 3.6864 MHz crystal, FLTIM should be set to 5. Chip Erase The Chip Erase instruction erases all data in the Flash memory, including the lock bits. All bits will be set high. Wait 450 ms (depending on Set Flash Timing) after sending the Chip Erase instruction before issuing a new instruction.
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Load Program Memory Page The Load Program Memory Page instruction is used to load the 128 bytes of data in a page to a buffer in RAM. Each instruction writes one byte to the 7 bit address specified in the instruction. Write Program Memory Page The Write Program Memory Page instruction writes the 128 bytes buffered through the Load Program Memory Page instructions to Flash memory. After issuing this command, wait 5.4 ms for it to complete. It is also possible to use the Read Program Memory instruction to poll when the program memory has been written. When writing is in progress, all read instructions will return 0xFF. Reading an address containing data different from 0xFF can then be used to check when the write is completed. Read Program Memory The Flash program memory can be read back byte by byte using the Read Program Memory instruction. The data is returned in byte 4 of the instruction. Wait at least 9 TXOSC between the last negative transition on SCK for byte 3 before issuing the first positive edge on SCK for byte 4 to receive valid data. Write Lock Bits The reading (through SPI) and writing to the Flash program memory can be disabled by setting the lock bits as described in this section. This should be used for software protection. The lock bits are set using the Write Lock Bits instruction. A block of programmable size at the top of the Flash program memory can be locked for writing using the LSIZE bits. Page 0 can be independently locked for writing by using the BBLOCK bit. Reading data through the SPI interface can be disabled using the SPIRE bit. The detailed description of all lock bits are given in Table 12.
SmartRF a CC1010
Table 12. Flash Lock Bits
Bit 7:3 4 Name BBLOCK Function Reserved, write as '0' Boot Block Lock 0 : Page 0 is write protected 1 : Page 0 is writeable, unless LSIZE is 000 Lock Size, sets the size of the upper Flash area which is write protected. Byte sizes and page numbers are listed below: 000 : 32768 (All pages) 001 : 16384 (page 128-255) 010 : 8192 (page 192-255) 011 : 4096 (page 224-255) 100 : 2048 (page 240-255) 101 : 1024 (page 248-255) 110 : 512 (page 252-255) 111 : 0 (no pages) SPI Read Flash Enable / Disable 0 : SPI Interface returns all zeros on the Read Program Memory instruction 1 : SPI Interface returns valid Flash data on the Read Program Memory instruction
3 2 1
LSIZE.2 LSIZE.1 LSIZE.0
0
SPIRE
Lock bits can only be erased (set high) by issuing the Chip Erase instruction. If multiple Write Lock Bits instructions are issued without chip erase in between, each lock bit will be AND-ed together with the previously written lock bits. In effect, this means that it is not possible to unlock the Flash program memory without also erasing it. The effect of the different Flash write lock bits are illustrated in Figure 6.
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Page number LSIZE = 001 LSIZE = 010 LSIZE = 011 LSIZE = 100 LSIZE = 101 LSIZE = 110 LSIZE = 000 LSIZE = 111
SmartRF a CC1010
Signature Byte instruction. The 3 bit signature byte address is issued, and the value is then returned as byte 4. Table 13. Signature Bytes
Signature byte address 000 001 010 011 100
101
UNLOCKED
0x7E00
LOCKED
LOCKED
0x7FFF
Address
0x7C00
0x7800
0x7000
0x6000
0x0000
2 1 0
UNLOCKED
0x4000
UNLOCKED
130 129 128 127 126
UNLOCKED
UNLOCKED
194 193 192 191 190
UNLOCKED
UNLOCKED
226 225 224 223 222
LOCKED
LOCKED
242 241 240 239 238
LOCKED
LOCKED
255 254 253 252 251 250 249 248 247 246
Value 0x7F 0x7F 0x7F 0x9E 0x95
0x00
Meaing JEDEC manufacturer ID, identifies Chipcon AS as the manufacturer. Identifies 32 kBytes of Flash memory Identifies CC1010
LOCKED
Wait at least 9 TXOSC between the last negative transition on SCK for byte 3 before issuing the first positive edge on SCK for byte 4 to receive valid data, as with the Read Program Memory instruction. SPI Flash Programming Initialisation
CC1010 must be set into the Flash programming mode to allow SPI Flash operations. This is done as follows:
* Apply power between all DVDD and DGND pins. Hold PROG low If a crystal is connected between
Page 0 is locked when BBLOCK is cleared
Figure 6. Flash Lock Bits illustration Read Lock Bits The lock bits described in the previous section can be read through the SPI interface by using the Read Lock Bits instruction. The instruction will return the 8 lock bits in byte 4 of the instruction. Wait at least 9 TXOSC between the last negative transition on SCK for byte 3 before issuing the first positive edge on SCK for byte 4 to receive valid data, as with the Read Program Memory instruction. The lock bits can only be read through the SPI interface, and not from the 8051 core. Read Signature Byte A 6 byte chip signature can be read through the SPI interface using the Read
* *
XOSC_Q1 and XOSC_Q2, hold RESET low and wait for the oscillator to start up. Crystal oscillator start-up times are
given in Table 4. Release RESET and wait at least 4 crystal oscillator periods. * If a crystal is not connected between
XOSC_Q1 and XOSC_Q2, hold RESET low and apply a clock signal to XOSC_Q1. Release RESET after at least 3 clock periods, and then wait at least 4 clock periods.
* Execute the Programming Enable instruction to complete the SPI Flash programming Initialisation.
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CC1010 is now ready to be programmed, as described in the next section.
Programming the Flash Memory After the initialisation is completed, SPI programming can be performed as follows: * * * Device identity can be verified using the Read Signature Byte instruction. Perform Chip Erase. Load one page into the buffer using the Load Program Memory Page instruction.
SmartRF a CC1010
* Write the buffer to Flash by using the Write Program Memory Page instruction. Repeat the loading and writing of each new page. Programming can be verified using the Read Program Memory instruction. Set the lock bits using the Write Lock Bits instruction. Lock bits can be verified by using the Read Lock Bits instruction.
* * * *
8051 Flash Programming Each of the 256 pages (128 bytes each) in Flash program memory can be programmed individually from the 8051. The 8051 must be set in Idle Mode while programming the Flash, since it has no access to the program memory while the writing is in progress. The step for writing a page to Flash is described as follows: * Set the correct write cycle time, according to the current crystal oscillator frequency, in the FLTIM SFR. This number is used to generate the timing to the on-chip Flash interface, as was also done with SPI Flash programming. It must be set so that: * * * Write the desired Flash page number to the FLADR register. Disable all interrupts except the Flash / Debug interrupt, which must be enabled (through EICON.FDIE) Store the 128 bytes of data to be written in the external data memory. The address of the first byte in the bufffer must be a multiple of 128. Write the 4 most significant bits of the RAM buffer address to FLCON.RMADR(3:0). Also set the bit FLCON.WRFLASH Set the 8051 in Idle Mode by setting PCON.IDLE. The Flash page is then autmatically erased and programmed.
*
*
f XOSC f FLTIM XOSC 0.8MHz 0.4 MHz
* The time used for programming a Flash page is strongly dependent on the setting in FLTIM. It is therefore recommended to set FLTIM as low as possible, as with the SPI Flash programming.
The sequence of the above steps are not important. Flash programming is started whenever entering Idle Mode while FLCON.WRFLASH is set. A Flash / Debug interrupt will be generated when the page write operation is completed, which will get the 8051 out of Idle Mode. An ISR must be present to service the Flash / Debug interrupt.
FLADR (0xAE) - Flash Write Address Register
Bit 7:0 Name
FLADR(7:0)
R/W R/W
Description The number of of the Flash page to be written (8 MSB of the byte address)
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FLCON (0xAF) - Flash Write Control Register
Bit 7 6:5 Name
SmartRF a CC1010
FLASH_LP (1:0)
R/W R0 R/W
4
WRFLASH
R/W
3:0
RMADR(3:0)
R/W
Description Reserved, read as 0 Flash Low Power control bits 00 : The Flash module is always active. 01 : The Flash module enters standby mode when the 8051 is put in Idle mode or Stop mode 10 : The Flash module enters standby mode between instruction fetches and when the 8051 is put in Idle Mode or Stop Mode. 11 : Reserved for future use. Write Flash Start bit Starting a Flash page programming is done by first setting this bit and then setting the 8051 in Idle Mode. If the WRFLASH bit is cleared before Idle Mode is entered, no programming is performed. RAM Buffer address RMADR(3:0) contains the 4 most significant bits of the RAM address where the data is buffered before writing to Flash
FLTIM (0xDD) - Flash Write Timing Register
Bit 7:0 Name
FLTIM(7:0)
R/W R/W
Description Flash Write Timing control FLTIM must be set as described in this section prior to using the 8051 Flash programming.
If an attempt is made to write data to a Flash page which is locked (see the previous section), a Flash / Debug interrupt will be generated immediately after Idle Mode is entered. No data will be written. It is not possible to read or write the Flash lock bits from the 8051.
Example Code An example code writing data buffered at address 0x100-0x17F in external RAM to the second page in Flash (address 0x0800x0FF) is shown below.The system clock frequency is assumed to be 3.6864 MHz. An interrupt service routine must be present at address 0x33, which clears the interrupt flag EICON.FDIF and returns from the interrupt (RETI).
FLTIM=0x05; /* FLADR=0x01; /* EICON|=0x20; /* IE&= ~0x80; /* FLCON=0x10 | (0x100 /* PCON|=0x01; /*
Set Flash timing for 3.6864 MHz clock frequency */ Write data to the second page in Flash */ Enable Flash interrupt */ Disable other interrupts */ >> 7); Enable Flash writing, RAM buffer from addr. 0x100 */ Enter Idle Mode to start Flash writing.
Flash Power Control The Flash module can be set into different power modes using the control bits FLCON.FLASH_LP(1:0) introduced in the previous section. After reset, the Flash module is always active, drawing a static current of approximately 2.5 mA (at nominal operating conditions). However, to save power the Flash module can be set in a power-down mode between instructions in Active mode, and always in Idle or PowerDown mode. This will save approximately
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1.5 mA of the Flash current consumption during operation in Active mode, and 2.5
SmartRF a CC1010
mA during Idle or Power-Down mode.
In Circuit Debugging In order to facilitate a software monitor for in-circuit debugging/emulation capabilities a number of hardware support features have been implemented: A breakpoint instruction has been added to the 8051's instruction set. The instruction, given the mnemonic TRAP, is a single byte instruction with the opcode 0xA5. In the original 8051 the 0xA5 opcode executed as a NOP instruction (opcode 0x00.) In the modified core this instruction raises a highest-level interrupt (Flash / Debug) by setting the corresponding interrupt flag EICON.FDIF and waiting a sufficient number of instruction cycles to allow the interrupt to take effect before the next instruction. The TRAP instruction can thus be written over the first byte (opcode) of any other instruction, the execution of which then will result in a branch to a software debugging monitor in the highest priority interrupt service routine. Single-stepping through instructions is supported since exactly one instruction is executed if an interrupt condition exists when returning from an interrupt service routine. Thus, single-stepping can be accomplished simply by not clearing the corresponding interrupt flag in the interrupt service routine associated with the software monitor. A second serial port has been added to enable debugging communication with a host PC without disrupting applications who use the main serial port for other purposes. Setting breakpoints and executing the instructions which have a breakpoint attached involves writing new data to the Flash instruction memory several times. Since the Flash memory can only withstand 20000 (typical) erase/writecycles a simple instruction replacement mechanism has been implemented. This feature allows the surveillance of an address in the instruction memory space as defined in registers RADRL and RADRH. When this address is encountered on the Flash program memory address bus, the data returned on the data bus is replaced by the contents of register RDATA. Setting RADRH=RADRL=0 disables the replacement mechanism. This instruction replacement mechanism can be used in different ways: * A simple way of setting a single soft (not stored in FLASH) breakpoint, by setting RDATA to 0xA5 (the TRAP instruction) and RADR to the breakpoint address. A simple way of restoring the original opcode byte of an instruction which has been subjected to a hard (stored in Flash) breakpoint, so that it can be executed (in single-step mode). SFRs (hardware registers) can normally only be addressed directly (i.e. by hardwiring the specific address into the corresponding MOV instruction.) This would make code in a debug monitor, which returns the value of SFRs to a PC rather bloated. Using the instruction replacement mechanism on the operand byte of the move instruction instead of the opcode byte, allows indirect addressing of SFRs.
*
*
Chipcon provides software for in-circuit debugging, which may be downloaded from the Chipcon homepage. This software uses the RESERVED register, which can then not be used for other purposes. If in-circuit debugging is not required, the RESERVED register shown below may be used for any purpose. Writing to it will have no effect on the operation of CC1010.
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Great caution should be used when the RADR is written. As the address consist of two bytes (RADRL and RADRH) there will be a short interval where the address is not valid as only one of the bytes are written at a time. If this intermediate
SmartRF a CC1010
address point to the very same location as of the code modifying the RADR, a malfunction will occur. One possible workaround is to first write RADRH to a value pointing to a memory location not used by the code.
RESERVED (0xE7) - Reserved register, used by Chipcon debugger software
Bit 7:0 Name
RESERVED(7:0)
R/W R/W
Description Reserve register, which is used by Chipcon debugger software. RESERVED may be used for other purposes if Chipcons debugger software is not needed.
RDATA (0xB9) - Replacement Data
Bit 7:0 Name
RDATA(7:0)
R/W R/W
Description Replacement data. Used to replace the byte at program memory address RADR with the data from RDATA, if RADR > 0.
RADRH (0xBB) - Replacement address, high byte
Bit 7:0 Name
RADR(15:8)
R/W R/W
Description Replacement address, high byte. Used to replace the byte at program memory address RADR with the data from RDATA, if RADR > 0.
RADRL (0xBA) - Replacement address, low byte
Bit 7:0 Name
RADR(7:0)
R/W R/W
Description Replacement address, low byte. Used to replace the byte at program memory address RADR with the data from RDATA, if RADR > 0
Chip Version / Revision
CC1010 has a SFR register CHVER which can be read to decide the chip type and
current revision. The register description is shown below.
CHVER (0x9F) - Chip Version / Revision Register
Bit 7:2 Name
CHIP_TYPE
R/W R
Description
CHIP_TYPE is a read only status word, which gives the type
number of the chip. 000000 : CC1010 000001 - 111111 : Reserved for future use CHIP_REV is a read only status word, which gives the chip revision number of the chip. Current chip revision is 01
1:0
CHIP_REV
R
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8051 Peripherals
CC1010 offers the following peripherals units controlled by the 8051 core:
* * * * Four general purpose I/O ports, with a total of 26 I/O pins. Two standard 8051 timers Two timers with PWM functionality Watchdog timer
SmartRF a CC1010
* * * * *
Realtime clock SPI master Hardware DES encryption / decryption Random bit generator 10 bit ADC
These modules are described in the following sections.
General Purpose I/O Four general purpose I/O-ports are available: P0, P1, P2 and P3. Table 5 shows each port and the pins on each port. Each port is associated with two registers: The port register (P0, P1, P2, or P3) and the direction register (P0DIR, P1DIR, P2DIR, or P3DIR). Each bit in the Px registers has its associated bit in the direction registers PxDIR. Setting PxDIR.y will make Px.y an input which can be read in Px(y). All pins are inputs after reset. Clearing PxDIR.y will make the pin Px.y output the data from the register Px(y). All Px and PxDIR register descriptions are shown from page 45. The structure for a single I/O-bit y on port x is shown in Figure 7. Some ports have alternate functions (such as the SPI interface), which are enabled through other registers (such as SPCR.SPE). These alternate functions may or may not override the direction setting from PxDIR as shown. When reading the Px registers, data is read from the pad. When using a read-modify-write instruction such as ANL Px, #0x01, the output register value is read and modified regardless of the setting in PxDIR. The CC1010 ports deviate from the standard 8051-port in the following ways: * * * No pull ups / pull downs on pins Dedicated direction bits in PxDIR registers CMOS output on all ports
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Table 14. Available I/O-Ports
Port Available pins Normal operation SCK, SPI Serial Clock output MO, SPI Master Output MI, SPI Master Input
SmartRF a CC1010
P0
P1
P2
P0.0 P0.1 P0.2 P0.3 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5
-
RXD1, Serial port 1 input TXD1, Serial port 1 output
-
RXD0, Serial port 0 input TXD1, Serial port 0 output INT0, External interrupt 0
Alternate Function Flash Programming SCK, SPI Serial Clock Input SI, SPI Slave Input SO, SPI Slave Output -
P3
INT1, External interrupt 1 T0, Counter input 0 to Timer 0, or PWM2, PWM output from Timer 2 T1, Counter input 1 to Timer 1, or PWM3, PWM output from Timer 3
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Alternate function enable Alternate function static direction or PxDIR.y PxDIR.y Alternate data Read output register enable
SmartRF a CC1010
1 0
S
1
S
Internal Data Bus
D
Q Output register
Px.y PAD
0
Read Pin Enable
Figure 7. Port x bit y structure P0 (0x80) - Port 0 Data Register
Bit 7 6 5 4 3 2 1 0 Name
P0_3 P0_2 P0_1 P0_0
R/W R0 R0 R0 R0 R/W R/W R/W R/W
Description Reserved, read as 0 Reserved, read as 0 Reserved, read as 0 Reserved, read as 0 Data of port 0, bits 0 to 3.
P1 (0x90) - Port 1 Data Register
Bit 7 6 5 4 3 2 1 0 Name
P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Data of port 1, bits 0 to 7.
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P2 (0xA0) - Port 2 Data Register
Bit 7 6 5 4 3 2 1 0 Name
SmartRF a CC1010
P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Data of port 2, bits 0 to 7
P3 (0xB0) - Port 3 Data Register
Bit 7 6 5 4 3 2 1 0 Name
P3_5 P3_4 P3_3 P3_2 P3_1 P3_0
R/W R0 R0 R/W R/W R/W R/W R/W R/W
Description Reserved, read as 0 Reserved, read as 0 Data of port 3, bits 0 to 5
P0DIR (0xA4) - Port 0 Direction Register
Bit 7 6 5 4 3 2 1 0 Name
P0DIR_3 P0DIR_2 P0DIR_1 P0DIR_0
R/W R0 R0 R0 R0 R/W R/W R/W R/W
Description Reserved, read as 0 Reserved, read as 0 Reserved, read as 0 Reserved, read as 0 Port 0 direction register, bit 0 to 3. Each bit sets the direction of the associated pin on Port 0. 0 : Associated pin is an output 1 : Associated pin is an input
P1DIR (0xA5) - Port 1 Direction Register
Bit 7 6 5 4 3 2 1 0 Name
P1DIR_7 P1DIR_6 P1DIR_5 P1DIR_4 P1DIR_3 P1DIR_2 P1DIR_1 P1DIR_0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Port 1 direction register, bit 0 to 7. Each bit sets the direction of the associated pin on Port 1. 0 : Associated pin is an output 1 : Associated pin is an input
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P2DIR (0xA6) - Port 2 Direction Register
Bit 7 6 5 4 3 2 1 0 Name
SmartRF a CC1010
P2DIR_7 P2DIR_6 P2DIR_5 P2DIR_4 P2DIR_3 P2DIR_2 P2DIR_1 P2DIR_0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Port 2 direction register, bit 0 to 7. Each bit sets the direction of the associated pin on Port 2. 0 : Associated pin is an output 1 : Associated pin is an input
P3DIR (0xA7) - Port 3 Direction Register
Bit 7 6 5 4 3 2 1 0 Name
P3DIR_5 P3DIR_4 P3DIR_3 P3DIR_2 P3DIR_1 P3DIR_0
R/W R0 R0 R/W R/W R/W R/W R/W R/W
Description Reserved, read as 0 Reserved, read as 0 Port 3 direction register, bit 0 to 7. Each bit sets the direction of the associated pin on Port 3. 0 : Associated pin is an output 1 : Associated pin is an input
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Timer 0 / Timer 1
SmartRF a CC1010
CC1010 contains two standard 8051 timers/counters (Timer 0 and Timer 1) which can operate as either a timer with a clock rate based on the system clock (as defined by the current clock mode), or as an event counter clocked by the T0 (P3.4 for Timer 0) or T1 (P3.5 for Timer 1) inputs.
Each Timer / Counter has a 16-bit register which is readable and writeable through TL0 and TH0 for Timer / Counter 0 and TL1 and TH1 for Timer / Counter 1. These registers are described below.
TL0 (0x8A) - Timer / Counter 0 Low byte counter value
Bit 7:0 Name
TL0(7:0)
R/W R/W
Description Timer / Counter 0, low byte counter value
TL1 (0x8B) - Timer / Counter 1 Low byte counter value
Bit 7:0 Name
TL1(7:0)
R/W R/W
Description Timer / Counter 1, low byte counter value
TH0 (0x8C) - Timer / Counter 0 High byte counter value
Bit 7:0 Name
TH0(7:0)
R/W R/W
Description Timer / Counter 0, high byte counter value
TH1 (0x8D) - Timer / Counter 1 High byte counter value
Bit 7:0 Name
TH1(7:0)
R/W R/W
Description Timer / Counter 1, high byte counter value
Timer / Counter 0 and 1 Modes Timer / Counter 0 and 1 can individually be programmed to operate in one out of four different modes, controllable through the registers TMOD and TCON. They are as follows: * 13-bit timer / counter (Mode 0)
* * *
16-bit timer / counter (Mode 1) 8-bit timer / counter with auto-reload (Mode 2) Two 8-bit timers / counters (Mode 3, Timer 0 only)
See the register descriptions for TMOD and TCON on the following pages.
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SmartRF a CC1010
TMOD (0x89) - Timer / Counter 0 and 1 Mode register
Bit 7 Name
GATE1
R/W R/W
Description Timer / Counter 1 gate control 0 : Timer / Counter 1 will clock only when TCON.TR1 is set. 1 : Timer / Counter 1 will clock only when TCON.TR1 is set and
the INT1 input is high. Counter / Timer select for Counter / Timer 1 0 : Timer 1 is clocked by the system clock divided by 4 or 12, depending on the state of CKCON.T1M (see page 51) 1 : Timer 1 is clocked by the T1 pin. Timer / Counter 1 mode select bits 00 : 13-bit counter 01 : 16-bit counter 10 : 8-bit counter with auto-reload 11 : Timer 1 off Timer / Counter 0 gate control 0 : Timer / Counter 0 will clock only when TCON.TR0 is set. 1 : Timer / Counter 0 will clock only when TCON.TR0 is set and the INT0 input is high. Counter / Timer select for Counter / Timer 0 0 : Timer 0 is clocked by the system clock divided by 4 or 12, depending on the state of CKCON.T0M (see page 51) 1 : Timer 0 is clocked by the T0 pin. Timer / Counter 0 mode select bits 00 : 13-bit counter 01 : 16-bit counter 10 : 8-bit counter with auto-reload 11 : Two 8-bit counters
6
C/T1
R/W
5 4
M1.1 M1.0
R/W R/W
3
GATE0
R/W
2
C/T0
R/W
1 0
M0.1 M0.0
R/W R/W
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SmartRF a CC1010
TCON (0x88) - Timer / Counter 0 and 1 control register
Bit 7 Name
TF1
R/W R/W
6 5
TR1 TF0
R/W R/W
4 3
TR0 IE1
R/W R/W0
Description Timer 1 overflow flag. TF1 is set to 1 by hardware when the Timer 1 count overflows and is cleared by hardware when the 8051 vectors to the interrupt service routine. Timer 1 run control bit 0 : Timer / Counter 1 is disabled 1 : Timer / Counter 1 is enabled Timer 0 overflow flag. TF0 is set to 1 by hardware when the Timer 0 count overflows and is cleared by hardware when the 8051 vectors to the interrupt service routine. Timer 0 run control bit 0 : Timer / Counter 0 is disabled 1 : Timer / Counter 0 is enabled External interrupt 1 edge detect (interrupt flag)
If external interrupt 1 is configured to be edge sensitive (TCON.IT1 = 1), IE1 is set by hardware when a negative edge is detected on the INT1 pin and is cleared by hardware when the 8051 vectors to the corresponding interrupt service routine. In edge-sensitive mode, IE1 can also be set by software. If external interrupt 1 is configured to be level-sensitive (TCON.IT1 = 0), IE1 is set when the INT1 pin is low and cleared when the INT1 pin is high. In level-sensitive mode, software cannot write to IE1. External interrupt 1 type select. 0 : The INT1 interrupt is triggered when INT1 is low (level sensitive). 1 : The INT1 interrupt is triggered on the falling edge (edge sensitive) External interrupt 0 edge detect (interrupt flag) If external interrupt 0 is configured to be edge sensitive (TCON.IT0 = 1), IE0 is set by hardware when a negative edge is detected on the INT0 pin and is cleared by hardware when the 8051 vectors to the corresponding interrupt service routine. In edge-sensitive mode, IE0 can also be set by software. If external interrupt 0 is configured to be level-sensitive (TCON.IT0 = 0), IE0 is set when the INT0 pin is low and cleared when the INT0 pin is high. In level-sensitive mode, software cannot write to IE0. External interrupt 0 type select. 0 : The INT0 interrupt is triggered when INT0 is low (level sensitive). 1 : The INT0 interrupt is triggered on the falling edge (edge sensitive)
2
IT1
R/W
1
IE0
R/W0
0
IT0
R/W
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SmartRF a CC1010
CKCON (0x8E) - Timer Clock rate Control Register
Bit 7 6 5 4 Name
T1M
R/W TBD TBD TBD R/W
3
T0M
R/W
2:0
MD(2:0)
R/W
Description Reserved Reserved Reserved Timer 1 clock select. T1M has no effect in counter mode. 0 : Timer 1 uses the C clock divided by 12 (for compatibility with the 80C32) 1 : Timer 1 uses the C clock divided by 4 Timer 0 clock select. T0M has no effect in counter mode. 0 : Timer 0 uses the C clock divided by 12 (for compatibility with the 80C32) 1 : Timer 0 uses the C clock divided by 4 MD(2:0) controls the memory stretch cycles when accessing the external RAM. The reset value is 001, but for faster access to external RAM, MD(2:0) should always be written 000.
Mode 0 Mode 0 operation is illustrated for timer or counter 0 and 1 in Figure 8. The timer / counter uses bit 0 to 4 of TL0 / TL1 and all 8 bits of TH0 / TH1 as a 13 bit counter. TCON.TR0 / TCON.TR1 must be set to enable the Timer / Counter. The C/T bit in TMOD selects the Timer or Counter clock source as described. Transitions are counted from the selected source, as long as TMOD.GATE0 / TMOD.GATE1 is 0, or TMOD.GATE0 /
Divide by 12 System Clk Divide by 4 T0 / T1 1 0 T0M / T1M 0 1 C/T0 / C/T1
TMOD.GATE1 is 1 and the corresponding
interrupt pin ( INT0 / INT1 ) is deasserted. When the 13-bit count increments from 0x1FFF (all ones), the counter rolls over to all zeros. The overflow flag TCON.TF0 / TCON.TF1 is then set. The 3 most significant bits in TL0 / TL1 are undetermined in Mode 0, and should be masked by software for evaluation.
TL0 / TL1 TR0 / TR1 Clock 0 1 2 3 4 5 6 7
Mode 0 GATE0 / GATE1 Mode 1 INT0 / INT1 TH0 / TH1 0 1 2 3 4 5 6 7
TF0 / TF1
Timer 0 / Timer 1 interrupt request
Figure 8. Mode 0 and Mode 1 operation for Timer / Counter 0 or 1
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Mode 1 Mode 1 operation is illustrated for Timer / Counter 0 and 1 in Figure 8. The counter is configured as a 16 bit counter, as compared to the 13 bits in Mode 0, and all bits in TL0 or TL1 are thus used. The counter overflows when the count increments from 0xFFFF. Otherwise, Mode 1 operation is the same as Mode 0.
Divide by 12 System Clk Divide by 4 T0 / T1 1 0 T0M / T1M 0 1 C/T0 / C/T1
SmartRF a CC1010
Mode 2 Mode 2 operation is illustrated for Timer / Counter 0 and 1 in Figure 9. Mode 2 operates as an 8 bit counter with automatic reload of the start value. The Timer / Counter is controlled as for Mode 0 and Mode 1, but when TL0 / TL1 overflows, TH0 / TH1 is loaded into TL0 / TL1.
TL0 / TL1 TR0 / TR1 Clock Mux GATE0 / GATE1 TH0 / TH1 INT0 / INT1 Reload
TF0 / TF1
Timer 0 / Timer 1 interrupt request
Figure 9. Mode 2 operation for Timer / Counter 0 or 1 Mode 3 In Mode 3, which is illustrated in Figure 10, Timer 0 is operated as two separate 8-bit counters and Timer 1 stops counting and holds its value. or 12 (as given by CKCON.T1M). TH0 may then generate Timer 1 interrupts. Timer 1 has limited usage when Timer 0 is in mode 3. This is because Timer 0 uses the Timer 1 control bit TR1 and the interrupt flag TF1. However, Timer 1 can still be used for baud rate generation and the Timer 1 count values are still available in the TL1 and TH1 registers. Control of Timer 1 when Timer 0 is in mode 3 is done through the Timer 1 mode bits. To turn Timer 1 on, set Timer 1 to mode 0, 1 or 2. To turn Timer 1 off, set it to mode 3. Timer 1 can count clock cycles divided by 4 or 12 or high to low transitions on the T1 pin. The GATE function is also available.
TL0 is configured as an 8 bit counter controlled by the normal Timer 0 control bits. It counts either clock cycles divided by 4 or by 12 (as given by CKCON.T0M), or high to low transitions on T0 (as given by
TMOD.C/T0 ). It is also possible to use the
GATE function for TL0 to set INT0 as count enable. TH0 is locked into a timer function, and takes over the use of TR1 and TF1 from Timer 1. It counts clock cycles divided by 4
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SmartRF a CC1010
TR1
Clock TH0 Divide by 12 0 T0M 1 0 C/T0 1 TF1 Timer 1 interrupt request
C Clk Divide by 4 T0
TL0 TR0 Clock
GATE0 TF0 INT0
Timer 0 interrupt request
Figure 10. Mode 3 operation for Timer / Counter 0
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Timer 2 / 3 with PWM
SmartRF a CC1010
CC1010 also features two timers with pulse width modulation (PWM) outputs. Each timer can generate interrupts, as described in the Interrupts section on page 26. The timers are individually set in one of two modes, timer mode or PWM mode. This is controlled through the bits M2 and
TCON2 (0xA9) - Timer Control register 2
Bit 7 6 5 4 3
2
M3 in the TCON2 control register shown below.
Timer 2 and Timer 3 are enabled individually through the bits TCON2.TR2 and TCON2.TR3.
Name
TR3 M3
R/W R0 R0 R0 R0 R/W
R/W
1 0
TR2 M2
R/W R/W
Description Reserved, read as 0 Reserved, read as 0 Reserved, read as 0 Reserved, read as 0 Timer 3 run control 0 : Timer 3 is disabled. The Timer 3 counter is cleared. 1 : Timer 3 is enabled. Timer 3 mode control. 0 : Timer 3 is in timer mode. 1 : Timer 3 is in PWM mode. P3.5 is set to be an output, overriding P3DIR(5) Timer 2 run control 0 : Timer 2 is disabled. The Timer 2 counter is cleared. 1 : Timer 2 is enabled. Timer 2 mode control. 0 : Timer 2 is in timer mode. 1 : Timer 2 is in PWM mode. P3.4 is set to be an output, overriding P3DIR(4)
Timer Mode Timer 2 / Timer 3 can be set in Timer Mode by clearing the bit TCON2.M2 / TCON2.M3. Timer Mode operation is illustrated in Figure 11. The 16 bit counter is preloaded with T2 and T2PRE (or T3 and T3PRE) as shown. When disabling the timer through clearing TCON2.TR2 (or TCON2.TR3) the counter is also preloaded. The counter value cannot be read by software. When the counter underflows (decrements from a zero value), it is loaded with the contents of T2 / T3 and T2PRE / T3PRE,
and the interrupt request bit EXIF.TF2 / EXIF.TF3 is set by hardware. The interrupt request must be cleared by software. In Timer mode, interrupts are generated with an interval as given by TnINT , where n{2,3} :
TnInt =
255 (TnPRE 256 + Tn + 1) f system
As long as TnPRE and Tn are set before TCON.TRn, the first interrupt is generated TnINT after enabling the timer and then with TnINT intervals.
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Timer 2 (or Timer 3) 16 bit counter System Clock Divide by 255 Clk 0 1 2 3 4 5 6 7 8
SmartRF a CC1010
Underflow
9 10 11 12 13 14 15
Mux 0 TR2 (or TR3) 1 2 3 4 5 6 7 0 1 2
Mux 3 4 5 6 7
EXIF.TF2 (or EXIF.TF3)
Timer 2 (or Timer 3) interrupt request
T2 (or T3)
T2PRE (or T3PRE)
Figure 11. Timer Mode operation for Timer 2 / Timer 3 T2PRE (0xAA) - Timer 2 Prescaler Control
Bit 7:0 Name
T2PRE(7:0)
R/W R/W
Description Timer 2 Prescaler Control. In Timer Mode, T2PRE sets the 8 most significant bits of the 16bit counter reload value. In PWM Mode, T2PRE sets the prescaler value which sets the PWM period.
T3PRE (0xAB) - Timer 3 Prescaler Control
Bit 7:0 Name
T3PRE(7:0)
R/W R/W
Description Timer 3 Prescaler Control. In Timer Mode, T3PRE sets the 8 most significant bits of the 16bit counter reload value. In PWM Mode, T3PRE sets the prescaler value which sets the PWM period.
T2 (0xAC) - Timer 2 Low byte counter value
Bit 7:0 Name
T2(7:0)
R/W R/W
Description In Timer Mode, T2 sets the 8 least significant bits of the 16-bit counter reload value. In PWM Mode T2 sets the PWM duty cycle.
T3 (0xAD) - Timer 3 Low byte counter value
Bit 7:0 Name
T3(7:0)
R/W R/W
Description In Timer Mode, T3 sets the 8 least significant bits of the 16-bit counter reload value. In PWM Mode T3 sets the PWM duty cycle.
PWM Mode Timer 2 /Timer 3 can be set in PWM Mode by setting the bit TCON2.M2 / TCON2.M3. The pins P3.4 / P3.5 are then enabled as outputs, overriding the port direction bit P3DIR.4 / P3DIR.5. The port direction is overridden independent of the timer run control bit TCON2.TR2 / TCON2.TR3. Interrupts are not generated in PWM mode.
P3.4 is the PWM output for timer 2, P3.5 is the PWM output for Timer 3.
The PWM operation is illustrated in Figure 13. The PWM period TnPWM for timer n is set by TnPRE:
TnPWM =
255 (TnPRE + 1) f system
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The PWM "high" state duration TnhPWM for timer n is set by Tn:
SmartRF a CC1010
This means that in PWM mode, setting Tn to 0 produces a constant low output and setting Tn to 255 produces a constant high output. The timing of the PWM outputs is illustrated in Figure 12.
TnhPWM =
Tn (TnPRE + 1) f system
TnPWM
PWMn Output
TnPWM
TnhPWM
TnhPWM
Timer 2 or Timer 3
Figure 12. PWM Timing illustration
System Clk
Divide by TnPRE + 1
8 bit counter (counts 0-254) A A>B? TnPWM B PWM output
Figure 13. PWM operation for Timer 2 / Timer 3
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Power On Reset (Brown-Out Detection) The Power On Reset functionality detects power-on and brown-out situations, and includes glitch immunity and hysteresis for noise and transient stability. The power on reset functionality is disabled using the dedicated POR_E pin. Grounding POR_E will disable the internal
SmartRF a CC1010
power on reset. An external power-onreset module should then be connected to the external RESET_N pin. The Power On Reset and Brown-Out Detection voltage levels are specified in the Electrical Specifications section at page 7.
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Watchdog Timer
SmartRF a CC1010
CC1010 includes an 8 bit watchdog timer which is clocked by the system clock. The clock is divided by a number in the range from 2048 to 16384, controllable through WDT.WDTPRE(1:0). The divided clock
WDT (0xD2) - Watchdog Timer Control Register
Bit 7 6 5 4 3 Name
controls an 8 bit timer, which generates system reset upon overflow. A block diagram for the Watchdog Timer is shown in Figure 14.
WDTSE WDTEN
R/W R0 R0 R0 R/W R/W
2
WDTCLR
R0/W
1:0
WDTPRE.1
R/W
Description Reserved, read as 0 Reserved, read as 0 Reserved, read as 0 Watchdog Timer Stop Enable, used to disable the watchdog timer Watchdog Timer Enable / Disable 0 : The watchdog timer is disabled 1 : The watchdog timer is enabled The watchdog timer is enabled after reset. To disable the watchdog timer, WDTSE must be used as described in this section. Watchdog timer clear signal. WDTCLR must periodically be set to prevent the watchdog timer from resetting the system. WDTCLR is cleared by hardware, and is thus always read 0. 0 : Normal watchdog operation 1 : Watchdog timer is cleared. Watchdog timer prescaler control. WDTPRE(1:0) controls the division of the main crystal oscillator clock to generate the watchdog timer clock. 00 : fWDT = fXOSC / 2048 01 : fWDT = fXOSC / 4096 10 : fWDT = fXOSC / 8192 11 : fWDT = fXOSC / 16384
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Clear
SmartRF a CC1010
Enable
System clock
Watchdog Prescaler
/16384
/2048
/4096
/8192
WDTPRE(1:0)
WDTCLR
Clear
Enable
8 Bit Watchdog Counter Overflow
WDTEN
System Reset
Figure 14. Watchdog Timer Setting different prescaler settings, combined with different Main Crystal Oscillator frequencies, generates reset at an interval of:
256 2 (11+WDTPRE ) f system
The intervals for the maximum and minimum clock frequencies are shown in Table 15 below.
Table 15. Watchdog Timer timing
WDTPRE.1
0 0 1 1
WDTPRE.0
0 1 0 1
Division Rate
2048 4096 8192 16384
Reset timing, given fXOSC = 3MHz 175 ms 350 ms 699 ms 1400 ms
Reset timing, given fXOSC = 24MHz 21.8 ms 43.7 ms 87.4 ms 175 ms
Disabling the Watchdog Timer The Watchdog Timer is enabled after system reset, through the Watchdog Timer enable flag WDT.WDTEN. To disable the Watchdog Timer, this flag must be cleared. However, clearing this flag requires the user to first set the flag WDT.WDTSE, and then clearing
WDT.WDTEN within 16 system clock periods (preferably in the next instruction).
If interrupts are enabled while disabling the Watchdog Timer, the user must make sure that WDT.WDTEN is actually cleared. This could for instance be done as follows:
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while (WDT & 0x08) { WDT |= 0x10; // Set WDTSE WDT &= ~0x08; // Clear WDTEN }
SmartRF a CC1010
Enabling the Watchdog Timer Enabling the Watchdog Timer is simply done by setting WDT.WDTEN. It does not require using the WDT.WDTSE control bit.
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Realtime Clock The realtime clock can generate interrupts with intervals ranging from 1 to 127 seconds. It is connected to the 32.768 kHz crystal oscillator, which is disabled after reset. It must be enabled as described in the Power section on page 31. An external 32.768 kHz clock signal can also be applied, as described. The interrupt interval is programmed in the range from 1 through 127 seconds by setting RTCON.RT(6:0). The timer is
SmartRF a CC1010
enabled by setting RTCON.RTEN. The first interrupt will be generated RT seconds after RTEN is set. The realtime clock interrupt must be enabled as described in the Interrupts section on page 26. The RTC oscillator circuit is shown in Figure 15. The loading capacitors values can be calculated as described for the main crystal oscillator at page 30.
RTCON (0xED) - Realtime Clock Control Register
Bit 7
6:0
Name
RTEN RT(6:0)
R/W R/W
R/W
Description Realtime Clock Enable / Disable 0 : Realtime Clock is disabled 1 : Realtime Clock is enabled Realtime Clock interrupt interval control. RT(6:0) gives the desired interrupt interval in seconds. RT(6:0) must be between 1 and 127.
XOSC32_Q2 XTAL 32.768 kHz C12 C13
XOSC32_Q1
Figure 15. RTC oscillator circuit
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Serial Port 0 and 1 Two serial ports, serial port 0 and 1, are implemented. They are controlled through the SCON0 and SCON1 control register. The data is buffered in SBUF0 and SBUF1. Serial port 0 may be used for general purpose serial communication. Timer 1 may be used to generate different baud rates. Serial port 1 is primarily for use with an in-circuit-debugger, but can also be used for general purpose serial communication. A block diagram is shown in Figure 16. The general-I/O ports that map to the same physical pins as the serial ports
SmartRF a CC1010
must be configured in a certain way in order to allow serial communication. This is summarized in Table 16. The mode is set in SCON0.SMx_0 / SCON1.SMx_0. To receive data, SCON0.REN_0 / SCON1.REN_1 must be enabled for the ports. Separate transmit and receive interrupt flags are available in SCON0.TI_0 / RI_0 and SCON1.TI_1 / RI_1. Note that the baud rate also depends on the Clock Mode selected (see page 32).
Data Bus
Write SBUF
Read SBUF
TXD0/TXD1
SBUF0/SBUF1 (Transmit)
SBUF0/SBUF1 (Receive)
Mode 0 Transmit
Load SBUF
RXD0/RXD1
Receive Shift Register
Interrupt Request RI_0/RI_1 TI_0/TI_1 SCON0/SCON1
Figure 16. Serial ports block diagram
Table 16. Configuration of general purpose I/O for UART0 and UART1
UART0 P3.0 x x
1 x
Mode 0 Mode 1-3 Mode 0 Mode 1-3
P3.1 1 x
1 1
P3DIR.0 1 1
0 x
P3DIR.1 0 x
0 0
UART1 P2.0 x x
1 x
P2.1 1 x
1 1
P2DIR.0 1 1
0 x
P2DIR.1 0 x
0 0
TX
RX
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SBUF0 (0x99) - Serial Port 0, data buffer
Bit 7:0 Name
SmartRF a CC1010
SBUF0(7:0)
R/W R/W
Description Serial Port 0, data buffer.
SBUF1 (0xC1) - Serial Port 1, data buffer
Bit 7:0 Name
SBUF1(7:0)
R/W R/W
Description Serial Port 1, data buffer
SCON0 (0x98) - Serial Port 0 Control Register
Bit 7
6
Name
SM0_0 SM1_0
R/W R/W
R/W
5
SM2_0
R/W
4 3 2
REN_0 TB8_0 RB8_0
R/W R/W R/W
Description Serial Port 0 mode bits, decoded as: SM0_0 SM1_0 Mode 0 0 0 (Synchronous half duplex) 0 1 1 (Asynchronous full duplex, start + stop bit) 1 0 2 (Asynchronous full duplex, start + stop bit, 9th data bit) 1 1 3 (Asynchronous full duplex, start + stop bit, 9th data bit) Multiprocessor communication enable. In modes 2 and 3 SM2_0 = 1 enables the multiprocessor communication feature: In mode 2 or 3 RI_0 will not be activated if the received 9th bit is 0. If SM2_0 = 1 in mode 1, RI_0 will only be activated if a valid stop bit is received. In mode 0 SM2_0 establishes the baud rate: when SM2_0 = 0 the baud rate is clk / 12; when SM2_0 = 1 the baud rate is clk / 4. Receive enable. When REN_0 = 1 reception is enabled.
Defines the state of the 9th data bit transmitted in modes 2 and 3. In modes 2 and 3 RB8_0 indicates the state of the 9th bit received. In mode 1 RB8_0 indicates the state of the received stop bit. In mode 0 RB8_0 is not used. Transmit interrupt flag. Indicates that the transmit data word has been shifted out. In mode 0 TI_0 is set at the end of the 8th data bit. In all other modes TI_0 is set when the stop bit is placed on the TXD0 pin. TI_0 must be cleared by the software. Receive interrupt flag. Indicates that a serial data word has been received. In mode 0 RI_0 is set at the end of the 8th data bit. In mode 1 RI_0 is set after the last sample of the incoming stop bit, subject to the state of SM2_0. In modes 2 and 3 RI_0 is set at the end of the last sample of RB8_0. RI_0 must be cleared by the software.
1
TI_0
R/W
0
RI_0
R/W
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SCON1 (0xC0) - Serial Port 1 Control Register
Bit 7
6
SmartRF a CC1010
Name
SM0_1 SM1_1
R/W R/W
R/W
5
SM2_1
R/W
4 3 2
REN_1 TB8_1 RB8_1
R/W R/W R/W
Description Serial Port 1 mode bits, decoded as: SM0_1 SM1_1 Mode 0 0 0 (Synchronous half duplex) 0 1 1 (Asynchronous full duplex, start + stop bit) 1 0 2 (Asynchronous full duplex, start + stop bit, 9th data bit) 1 1 3 (Asynchronous full duplex, start + stop bit, 9th data bit) Multiprocessor communication enable. In modes 2 and 3 SM2_1 = 1 enables the multiprocessor communication feature: In mode 2 or 3 RI_1 will not be activated if the received 9th bit is 0. If SM2_1 = 1 in mode 1 RI_1 will only be activated if a valid stop bit is received. In mode 0 SM2_1 establishes the baud rate: when SM2_1 = 0 the baud rate is clk / 12; when SM2_1= 1 the baud rate is clk / 4. Receive enable. When REN_1 = 1 reception is enabled.
Defines the state of the 9th data bit transmitted in modes 2 and 3. In modes 2 and 3 RB8_1 indicates the state of the 9th bit received. In mode 1 RB8_1 indicates the state of the received stop bit. In mode 0 RB8_1 is not used. Transmit interrupt flag. Indicates that the transmit data word has been shifted out. In mode 0 TI_1 is set at the end of the 8th data bit. In all other modes TI_1 is set when the stop bit is placed on the TXD1 pin. TI_1 must be cleared by the software. RI_1 - Receive interrupt flag. Indicates that a serial data word has been received. In mode 0 RI_1 is set at the end of the 8th data bit. In mode 1 RI_1 is set after the last sample of the incoming stop bit, subject to the state of SM2_1. In modes 2 and 3 RI_1 is set at the end of the last sample of RB8_1. RI_1 must be cleared by the software.
1
TI_1
R/W
0
RI_1
R/W
MODE 0 Serial mode 0 provides synchronous, halfduplex serial communication. For serial port 0, pin RXD0 (P3.0) is used for data input and output while TXD0 (P3.1) provides the bit clock for both transmit and receive. For serial port 1 the corresponding pins are RXD1 (P2.0) and TXD1 (P2.1). The serial mode 0 baud rate is set by SCON0.SM2_0 / SCON1.SM2_1. If this bit is cleared, the baud rate is the system clock divided by 4. If the bit is set, the system clock is divided by 12.
Data transmission begins when an instruction writes to the SBUF0 (or SBUF1) register. The serial port shifts the data byte out, LSB first, at the selected baud rate. Data recepion starts when SCON0.REN_0 / SCON1.REN_1 is set and the receive interrupt flag SCON0.RI_0 / SCON1.RI_1 is cleared. The bit clock is activated and the UART shifts data in on each rising edge of the bit clock, until 8 bits have been received. Immediately after the 8th bit is shifted in, the receive interrupt flag is set and reception stops until the software clears the flag.
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The clock output is high when the serial port is idle. In reception, data is shifted in on the rising edge of the clock. In transmission, each new bit is set on the falling edge of the clock. MODE1 Mode 1 provides standard asynchronous full duplex communication, using a total of 10 bits: 1 start bit, 8 data bits and 1 stop bit. For receive operations, the stop bit is stored in SCON0.RB8_0 (or SCON1.RB8_1). Data bits are received and transmitted with their LSB first. The baud rate for mode 1 is a function of timer 1 overflow. Each time the timer increments from its maximum count (0xFF), a clock pulse is sent to the baud rate circuit, to be further divided by 16 or 32 as set by PCON.SMOD0 / EICON.SMOD1 to give the baudrate:
SmartRF a CC1010
Table 17. Baudrate examples (SMODx=1)
Baudrate
57.6 19.2 9.6 4.8 2.4 1.2
T1M/TH1 Fxosc = 11.0592 Fxosc = MHz 14.7456 MHz 0/255 1/252 0/253 0/252 0/250 0/248 0/244 0/240 0/232 0/224 0/208 0/192
To transmit data in mode 1, write data to SBUF0 / SBUF1. Transmission is then performed on TXD0 / TXD1 in the following order: start bit, 8 data bits (LSB first) and then the stop bit. Reception begins on the falling edge of a start bit received on RXD0 / RXD1, if reception is enabled in SCON0.REN_0 / SCON1.REN_1. The data input is sampled 16 times per baud for any baud rate. Each bit decision is performed as a majority decision between 3 successive samples in the middle of each baud. If the majority decision is not equal to zero for the start bit, the serial port will stop reception and wait for a new start bit. When the majority decision is made for the stop-bit, the following conditions must be met: * *
Baud Rate =
2 SMODx Timer 1 overflow 32
As can be seen from the equation above, if both serial ports are in use simultaneously, the baud rate is equal or different by a factor 2. It is common to use Timer 1 in Mode 2 (8bit counter with auto-reload) for baud rate generation, although any timer mode can be used. The Timer 1 reload value is stored in the TH1 register, which makes the complete baudrate using mode 2:
Baud Rate = f system 2SMODx 32 (12 - 8 T1M) (256 - TH1)
RI_0 / RI_1 is 0
If SM2_0 / SM2_1 is set, the state of the stop bit must be one
T1M in the above equation is in register CKCON (see page 51), and controls the initial division in Timer 1 between 4 and 12.
Some example baudrates and reload values are shown in Table 17. The setting for other baud rates and oscillator frequencies can easily be found using the above equation.
If these conditions are met, the received data is buffered in SBUF0 / SBUF1, the received stop bit is stored in RB8_0 / RB8_1) and the receive interrupt flag is set. If not, the received data is lost and RB8_0 / RB8_1 and the receive interrupt flag remains unchanged. MODE2 Mode 2 provides asynchronous full-duplex communication using a total of 11 bits: 1 start bit, 8 data bits, a programmable 9th bit and 1 stop bit. The data bits are transmitted and received LSB first.
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The mode 2 baud rate is either fsystem/32 or fsystem/64, set by PCON.SMOD0 (or EICON.SMOD1). The baud rate is then:
SmartRF a CC1010
lost and RB8 and the receive interrupt flag remains unchanged. MODE 3 Mode 3 provides asynchronous, fullduplex communication, using a total of 11 bits (as with mode 2): 1 start bit, 8 data bits, a programmable 9th bit and 1 stop bit. The data bits are transmitted and received LSB first. Transmission and reception in mode 3 is identical to mode 2, except for the baud rate generation, which is identical to mode 1. Multiprocessor Communications The multiprocessor communication feature is enabled in mode2 and mode 3, when the SM2_0 / SM2_1 bit is set. The 9th bit received is then stored in RB8_0 / RB8_1 and the interrupt bit is only set if this bit is 1. An address byte can then be transmitted, with the 9th bit set, to generate an interrupt on all slaves. The slave(s) with the correct address (decoded in software) may then clear SM2_0 / SM2_1 to receive the rest of the data, which is transmitted with the 9th bit low. All other slaves will then ignore the data received.
2 SMODx Baud Rate = f system 64
To transmit data in mode 1, write data to SBUF0 / SBUF1. Transmission is then performed on pin TXD0 / TXD1 in the following order: start bit, 8 data bits (LSB first), 9th bit (from TB8_0 / TB8_1) and then the stop bit. The transmit interrupt flag TI_0 / TI_1 is set when the stop bit is placed on the transmit pin. Reception must be enabled by setting REN_0 / REN_1. It is then initiated by the falling edge of a start bit received on RXD0 / RXD1. The input pin is sampled 16 times per baud. Majority decision is made, as with mode 1. When the majority decision is made for the stop-bit, the following conditions must be met: * *
RI_0 / RI_1 is 0
If SM2_0 / SM2_1 is set, the 9th bit and the stop bit must be one.
If these conditions are met, the received data is buffered in SBUF0 / SBUF1, the received stop bit is stored in RB8_0 / RB8_1 and the receive interrupt flag RI_0 / RI_1 is set. If not, the received data is
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SPI Master The SPI master interface allows CC1010 to communicate with peripheral devices such as an external serial EEPROM interface. It has a programmable datarate up to 3 MHz, depending on the frequency of the crystal attached. The SPI master interface is controlled using the SPCR register shown below. Setting SPCR.SPE enables the SPI interface. Pins P0.0, P0.1 and P0.2 are then reconfigured as the serial clock output SCK, the serial data output pin MO and the serial data input pin MI. The direction bits set in P0DIR(0) and P0DIR(2) are then ignored, setting SCK SPCR (0xA1) - SPI Control Register
Bit
7
SmartRF a CC1010
as an output and MI as an input. The direction bit P0DIR(1) still determines the direction of the master data output pin MO. This allows the SPI master to communicate with a bidirectional data line. P0DIR(1) should then be cleared when transmitting and set when receiving data, with MO and MI connected together externally. For normal full-duplex operation of the SPI master, P0DIR(1) must be cleared to set MO as an output. Any other general purpose I/O-pin may be used for slave select signals to the peripheral modules.
Name
6 5 4 3
SPE DORD CPOL
R/W R0 R/W R/W0
R/W R/W
2
CPHA
R/W
Description Reserved, read as 0 Reserved, write 0 SPI Enable. 0 : SPI interface is disabled 1 : SPI interface is enabled Data Order 0 : Least significant bit (LSB) is transmitted / received first 1 : Most significant bit (MSB) is transmitted / received first Clock Polarity 0 : SCK has negative clock polarity 1 : SCK has positive clock polarity Clock Phase
0 : Data is output on DO when SCK goes from CPOL to CPOL and is sampled from DI when SCK goes from CPOL to CPOL 1 : Data is output on DO when SCK goes from CPOL to CPOL and is sampled from DI when SCK goes from CPOL to CPOL
1:0
SPR(1:0)
R/W
SPI Data Rate.
SPR(1:0) 00 : SCK clock frequency = fXOSC / 8 01 : SCK clock frequency = fXOSC / 16 10 : SCK clock frequency = fXOSC / 32 11 : SCK clock frequency = fXOSC / 64
SPDR (0xA2) - SPI Data Register
Bit 7:0 Name
SPDR(7:0)
R/W R/W
Description SPI Data Register Writing to SPDR when SPCR.SPE is set will initiate a data transmission. Reading SPDR will read the data input buffer, which is only updated after each completed transmission.
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SPSR (0xA3) - SPI Status Register
Bit 7:2 1
0
SmartRF a CC1010
Name
SPA WCOL
R/W R0 R
R
Description Reserved, read as 0 SPI Active status bit 0 : The SPI interface is currently not transmitting data 1 : The SPI interface is currently transmitting data Write collision flag. This flag is updated by hardware when SPDR is written. 0 : The previous write to SPDR did not generate a data collision. 1 : The previous write to SPDR generated a data collision
Writing data to SPDR when SPCR.SPE is set will initiate a data transmission. 8 bits are transmitted and received with the data order, clock polarity, clock phase and data rate as set by SPCR.DORD, SPCR.CPOL, SPCR.CPHA and SPCR.SPR. Reading data from SPDR will read the input buffer, which is only updated after each complete transmission. This means that a new byte can be written to SPDR before reading the newly received byte in order to maximise the data rate. If data is written to SPDR while a transmission is in progress, this is regarded as a collision. After each new byte written to SPDR, the write collision flag SPSR.WCOL is updated. If a collision occurs, the data written to SPDR is ignored
and the data must be written to SPDR again to be sent. It is also possible to check the SPI status bit, SPSR.SPA, before writing to SPDR to avoid collisions. This bit is set only when data is being transmitted. SPI timing, data order, clock polarity and clock phase are shown in Figure 17.
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SmartRF a CC1010
SPDR is written by 8051 here, while SPCR.SPE is active
SCK
(CPOL=0, CPHA=0)
SCK
(CPOL=0, CPHA=1)
SCK
(CPOL=1, CPHA=0)
SCK
(CPOL=1, CPHA=1)
MO / MI
DORD=0
0 7
1 6
2 5
3 4
4 3
5 2
6 1
7 0
MO / MI
DORD=1
SPSR.SPA SPDR read by 8051 Data received during last byte transmission SPSR.WCOL is set if SPDR is written here New data
Figure 17. SPI Data Flow
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DES Encryption / Decryption DES encryption / decryption is supported by hardware in CC1010. Blocks of data ranging from 1 to 256 bytes can be encrypted / decrypted in one operation by the DES module. Multiple encryption / decryption operations can also be used on larger data blocks. Encryption is the process of encoding an information bit stream to secure the data content. The DES algorithm is a common, simple and well-established encryption routine. An encryption key of 56 bits is used to encrypt the message. The receiver must use the exact same key to decrypt the message, otherwise garbage will be produced. The encryption and decryption operations in the DES algorithm are reverse operations with the same computational requirements. The operations produce the same number of output bytes as input bytes. The strength of an encryption algorithm is determined by the number of bits in the key, the more the better. The DES algorithm offers a low to medium level of security. If higher levels of security are required, a triple DES algorithm can be used. Triple DES can be achieved by running the DES algorithm three times sequentially using three different 56-bit encryption keys. The keys must be used in reverse order when decrypting. The DES algorithm works internally on entities of 8 bytes. The Output Feedback Mode (OFB) and Cipher Feedback Mode (CFB) are DES modes of operation that permit data lengths that are not a multiple of eight bytes. The operation mode is selected through the CRPCON.CRPMD control bit. The same DES mode of operation must be used both for encryption and decryption to yield correct results. CFB is recommended as it is more secure than OFB.
SmartRF a CC1010
is given by the register CRPKEY, containing the 8 most significant address bits. New keys are loaded only at the beginning of an encryption / decryption if CRPCON.LOADKEYS is set. If not, the same keys as used in the previous run will be used again. The DES keys do not contain parity bits. If DES keys with parity bits are given, the parity bits must be removed before performing encryption / decryption. The keys are therefore stored as 7 successive bytes in RAM. After running the DES, a output block O of length CRPCNT bytes is generated by encrypting / decrypting the input block I of same length as O using key K1 as follows:
O=EK1(I) O=DK1(I)
(encryption) (decryption)
CRPCON.ENCDEC should be cleared when encrypting data and set when decrypting data.
56 bit DES keys are stored in external RAM, as shown in Table 18. The location
The following is an example on how to use the single DES algorithm hardware in CC1010. First the 56-bit encryption key must be stored in the external RAM. Then the CRPKEY register must be written to point to the start of the encryption key. Note that the encryption key must start on a RAM address location divisible by 8. Then the data bit stream to encrypt must be stored in the external RAM. The data bit stream must consist of at least 1 byte up to a maximum of 256 bytes, and it must also start on a RAM address location divisible by 8. The CRPDAT register must be written to point to the start of the data bit stream, and CRPCNT must be written to give the number of bytes to be encrypted. CRPINI0, CRPINI1, Then the CRPINI2, CRPINI3, CRPINI4, CRPINI5, CRPINI6, CRPINI7 registers must be written to contain the DES initialisation vector used in the OFB and CFB modes of operation. For simplicity it can be set to all zeros. Note that the initialisation vector must be the same for both encryption and decryption to yield correct results. To initiate the encryption the CRPCON register must be written. The bits in this register select
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encryption/decryption, feedback mode, and DES interrupt enable. When the encryption has been completed, CRPCON.CRPEN goes low and the DES interrupt flag is set. The external RAM will Table 18. DES key location in RAM
Key K1
SmartRF a CC1010
now contain the encrypted data bit stream in the same location as the input data bytes were originally put. To perform the reverse operation, write CRPCON again with the CRPCON.ENCDEC bit set.
First RAM Location 8 CRPKEY
Last RAM Location 8 CRPKEY+6
Encryption / decryption is done in-place, i.e. each byte of data read from external RAM for encryption / decryption will be written back to the same location after encryption / decryption as described above. The input and output blocks must start on an address which is a multiple of eight. CRPDAT then gives the 8 most significant address bits to the first data byte. The encryption / decryption initialization vector should be written to registers CRPINI0 to CRPINI7. These registers must be written prior to encrypting / decrypting a new block of data, as they are modified by hardware. They should be left unchanged between multiple encryption / decryption operations for DES blocks larger than 256 bytes. A zero value initialisation vector can be used, or additional security can be effected by using the initialisation vector as an additional key.
Encryption / decryption is started when CRPCON.CRPEN is set. When the encryption / decryption is completed, CRPCON.CRPEN is cleared by hardware and the interrupt flag CRPCON.CRPIF is set. If CRPCON.CRPIE is set, the interrupt flag EXIF.ADIF is also set, which will generate an interrupt if EIE.ADIE is set. (See the Interrupts section on page 26 for details on interrupts.) The duration of a DES encryption / decryption operation is shown in Table 19. Accessing external RAM from the 8051 while encrypting / decrypting may delay the operation slightly since the access is multiplexed. DES keys stored in Flash memory will be protected by the Flash memory protection. For the security of the Flash protection, please refer to the disclaimer at the end of this document.
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Table 19. DES Encryption / Decryption duration
Mode Single DES
SmartRF a CC1010
Duration (clock cycles) 2+25#Data Bytes +21LOADKEYS
CRPCON (0xC3) - Encryption / Decryption Control Register
Bit 7 6
5
Name
CRPIE CRPIF
R/W R0 R/W
R/W
4
LOADKEYS
R/W
3 2 1 0
CRPMD ENCDEC TRIDES CRPEN
R/W R/W R/W0 R/W1
Description Reserved, read as 0 Encryption / Decryption interrupt enable flag. In order for CRPIF to raise an interrupt, EIE.ADIE must also be set. Encryption / Decryption interrupt flag. CRPIF is set by hardware when an encryption / decryption is completed. CRPIF must be cleared by software. Because the encryption /decryption shares an interrupt line with the ADC, EXIF.ADIF must also be cleared by software before exiting the interrupt service routine.. EXIF.ADIF should be cleared before CRPIF, so that the 8051 is ready to receive a new interrupt immediately after CRPIF is cleared. Enable / disable loading of keys at startup. 0 : New keys are not loaded at encryption / decryption startup. The same keys as used during the previous encryption / decryption will be used again. 1 : New keys are loaded from RAM at encryption / decryption startup. The key RAM location is given by CRPKEY. OFB / CFB Mode 0 : OFB (Output Feedback Mode) is selected 1 : CFB (Cipher Feedback Mode) is selected Encryption / Decryption select 0 : Encryption is selected 1 : Decryption is selected Reserved, write 0 Encryption / Decryption start and status bit. When set by software, encryption / decryption is initiated. It cannot be cleared by software, but will be cleared by hardware when the encryption / decryption is completed.
CRPKEY (0xC4) - Encryption / Decryption Key Location Register
Bit 7:0 Name
CRPKEY(7:0)
R/W R/W
Description
CRPKEY(7:0) gives the 8 most significant bits of the external
RAM location of the DES keys. The keys are located in RAM as given in Table 18.
CRPDAT (0xC5) - Encryption / Decryption Data Location Register
Bit 7:0 Name
CRPDAT(7:0)
R/W R/W
Description
CRPDAT(7:0) gives the 8 most significant bits of the external
RAM address of the first byte to be encrypted / decrypted. The 3 least significant address bits are all zeros.
CRPCNT (0xC6) - Encryption / Decryption Counter
Bit 7:0 Name
CRPCNT(7:0)
R/W R/W
Description
CRPCNT(7:0) gives the number of bytes to be encrypted / decrypted. If CRPCNT=0, 256 bytes are encrypted / decrypted.
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SmartRF a CC1010
CRPINIn, n{0..7} (0xB4-0xB7, 0xBC-0xBF) - DES Initialisation Vector
Bit 7:0 Name
CRPINIn (7:0)
R/W R/W
Description The 8 registers CRPINIn, n {0..7}, contains the 64 bit DES initialisation vector. Bits 8n-1 down to 8n are located in register
CRPINIn
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Random Bit Generation
SmartRF a CC1010
CC1010 can generate real random bit sequences to be used as encryption keys, seed for a software pseudo random generator or other purposes. The data is generated from amplifying noise in the RF receiver path.
To enable random bit generation, set RANCON.RANEN and clear RFMAIN.RX_PD. Wait at least 1 ms before reading data from RANCON.RANBIT. The period between reads should be at least 10 s for the data to be as random as possible.
For applications requiring guaranteed DC free data, software should process the generated data, for example by xor'ing two successive bits. The random data generated has a relatively white spectrum, but tones have been observed when the random bit generator has been enabled for more than one second. If this is not sufficient for the application to generate the random bits required, the random bit generator should be disabled and enabled following the procedure described above before generating more data.
RANCON (0xC7) - Random Bit Generator Control Register
Bit 7:2 1 Name
RANEN
R/W R0 R/W
0
RANBIT
R
Description Reserved, read as 0 Random Bit Generator Enable 0 : Random Bit Generator is disabled. 1 : Random Bit Generator is enabled. RFMAIN.RX_PD must also be cleared to generate random bits. RANBIT returns one random bit, generated from the RF receiver path.
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ADC The on-chip 10 bit ADC is controlled by the registers ADCON and ADCON2. Three analog pins can be sampled, controlled by ADCON.ADADR. This register is also used to select the AD1 pin as external reference (when using AD0). The analog reference voltage is controlled by ADCON.ADCREF. ADCON.AD_PD should be set when the ADC is not is use to save power. A conversion can be started 5 s after clearing the bit when using VDD or an external reference, or 100 s afterwards when using the internal 1.25V reference. The ADC can be operated in 4 modes controlled by ADCON.ADCM. Each ADC sample conversion takes 11 ADC clock cycles. In Clock Mode 1, when POWER.PMODE is set, the 32 kHz clock is applied directly to the ADC. In Clock Mode 0 the ADC clock input is derived from the main oscillator clock using the divider selected by ADCON2.ADCDIV. The register must be set so that the resulting ADC clock frequency is less than or equal to 250 kHz. In single-conversion mode each conversion is initiated by setting the ADCON.ADCRUN control bit. The ADC EXIF.ADIF and interrupt flags ADCON2.ADCIF are set by hardware if the 8 MSB of the latest sampled value is greater than or equal to the threshold value stored in the ADTRH register. An interrupt service routine is then executed if the interrupt enable flags EIE.ADIE and ADCON2.ADCIE are set. To always get an interrupt upon completion of a conversion, ADTRH should be set to 0. The ADCON.ADCRUN control bit is cleared by hardware when the conversion is finished.
SmartRF a CC1010
In the multi-conversion modes the ADC starts a new conversion every 11th ADC clock cycle. All multi-conversion modes can be stopped by clearing ADCON.ADCRUN, after which the ADC will abort its current conversion and then stop. In all modes an action is taken when the 8 MSB of the latest sample value is greater than or equal to the value written in ADTRH; these are: Multi-conversion, continuous. When the threshold comparison holds true (value ADTRH 4) an interrupt is generated and the corresponding interrupt service routine is then executed if the interrupt enable flags EIE.ADIE and ADCON2.ADCIE are set. The ADC will continue its conversions regardless of the result of the threshold comparison. To always get an interrupt upon completion of a conversion, ADTRH should be set to 0. Multi-conversion, stopping. When the threshold comparison holds true (value ADTRH 4) an interrupt is generated and the corresponding interrupt service routine is then executed if the interrupt enable flags EIE.ADIE and ADCON2.ADCIE are set. The ADC will stop when the threshold comparison holds true, clearing ADCON.ADCRUN. Multi-conversion, reset-generating. When the threshold comparison holds true (value ADTRH 4) a system reset is generated. This mode can be used in conjunction with the 8051's stop mode and the 32 kHz oscillator to achieve very low power consumptions while monitoring a signal. The value stored in ADDATH and ADDATL are not affected by a reset, such that the sampled value can be read back after the reset has taken effect.
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ADCON (0x93) - ADC Control Register
Bit 7
6 5:4
SmartRF a CC1010
Name
AD_PD ADCM(1:0)
R/W R/W
R0 R/W
Description ADC Power down bit. 0 : ADC is active 1 : ADC is in power down Reserved, read as 0
ADC Mode: 00 : Single-conversion mode. (Interrupt when threshold condition holds true, stop after one conversion.) 01 : Multi-conversion mode, continuous. (Interrupt when threshold condition holds true, continue sampling.) 10 : Multi-conversion mode, stopping. (Interrupt when threshold condition holds true, stop sampling.) 11: Multi-conversion mode, reset-generating. (Generate reset when threshold condition holds true.) Select the internal ADC Voltage Reference 0 : Voltage reference is VDD 1 : Voltage reference is 1.25 V, generated on chip. ADC run control. Setting this bit in software will start ADC operation in single- or multi-conversion mode. In single conversion mode this bit is cleared by hardware when the single conversion is done. Multi-conversion operation can be halted at the end of the current conversion by clearing this bit. (When ADCM=10 the hardware clears this bit when stopping.) Select the analog input to the ADC 00 : Mux data from the AD0 pin 01 : Mux data from the AD1 pin 10 : Mux data from the AD2 (RSSI/IF) pin 11 : Mux data from the AD0 pin with AD1 as an external reference. ADCREF is ignored in this setting
3 2
ADCREF ADCRUN
R/W R/W
1:0
ADADR(1:0)
R/W
ADDATL (0x94) - ADC Data Register, Low Byte
Bit 7:0 Name
ADDAT(7:0)
R/W R
Description 8 LSB of ADC data output
ADDATH (0x95) - ADC Data Register, High Bits
Bit 7:2 1:0 Name
ADDAT(9:8)
R/W R0 R
Description Reserved, read as 0 2 MSB of ADC data output, latched when ADDATL is read
Chipcon AS
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ADCON 2(0x96) - ADC Control Register 2
Bit 7
6
SmartRF a CC1010
Name
ADCIE ADCIF
R/W R/W
R/W
5:0
ADCDIV
R/W
Description ADC interrupt enable flag. In order for ADCIF to raise an interrupt, EIE.ADIE must also be set. ADC interrupt flag. ADCIF must be cleared by software. Because the ADC shares an interrupt line with the DES module, EXIF.ADIF must also be cleared by software before exiting the interrupt service routine. EXIF.ADIF should be cleared first so that the 8051 is ready to receive a new interrupt immediately after ADCIF is cleared. ADC clock divider. Selects ADC clock divider in steps of 16. 000000: Divider is 16 000001: Divider is 32 ... 111111: Divider is 1024
ADTRH (0x97) - ADC Threshold Register
Bit 7:0 Name
ADTRH(7:0)
R/W R/W
Description ADC comparator threshold value, used to generate ADC interrupt or chip reset when the threshold is exceeded, as described.
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
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Chipcon
RF Transceiver
General description The CC1010 UHF RF Transceiver is designed for very low power and low voltage applications. The transceiver circuit is mainly intended for the ISM (Industrial, Scientific and Medical) and SRD (Short Range Device) frequency bands at 315, 433, 868 and 915 MHz, but can easily be programmed for operation at other frequencies in the 300-1000 MHz range. RF Transceiver Block Diagram
AD2(RSSI/IF)
SmartRF a CC1010
The main operating parameters of CC1010 can be programmed via Special Function Registers (SFRs), thus making CC1010 a very flexible and easy to use transceiver. Very few external passive components are required for operation of the RF Transceiver. The key parameters for the RF transceiver are listed in Table 4, page 7.
MIXER
RF_IN
LNA
IF STAGE
DEMOD
RFBUF
Internal 8051 SFR Bus
ENCODER
SFR CONTROL REGISTERS
RF_OUT
PA
/N BIAS VCO
R_BIAS XOSC_Q2 XOSC_Q1
~
L1 L2
LPF
CHARGE PUMP
PD
/R
OSC
CHP_OUT
Figure 18. Simplified block diagram of the RF Transceiver A simplified block diagram of the RF transceiver is shown in Figure 18. Only analog signal pins are shown together with the internal SFR data bus that is used to configure the RF interface and to transmit and receive data. In receive mode the CC1010 is configured as a traditional superheterodyne receiver. The RF input signal is amplified by the low-noise amplifier (LNA) and converted down to the intermediate frequency (IF) by the mixer (MIXER). In the intermediate frequency stage (IF STAGE) this downconverted signal is amplified and filtered before being fed to the demodulator (DEMOD). As an option a RSSI signal or the IF signal after the mixer is available at
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the AD2(RSSI/IF) pin. After demodulation the digital data is sent to the RFBUF register. Interrupts can be generated for each bit or byte received (EXIF.RFIF). In transmit mode the voltage controlled oscillator (VCO) output signal is fed directly to the power amplifier (PA). The RF output is frequency shift keyed (FSK) by the digital bit stream fed to the RFBUF register. Interrupts can be generated for each bit or byte to be transmitted (EXIF.RFIF). The internal T/R switch circuitry makes the antenna interface and matching very easy using a few passive components.
SmartRF a CC1010
The frequency synthesiser generates the local oscillator signal which is fed to the MIXER in receive mode and to the PA in transmit mode. The frequency synthesiser consists of a crystal oscillator (XOSC), phase detector (PD), charge pump (CHARGE PUMP), internal loop filter (LPF), VCO, and frequency dividers (/R and /N). An external crystal must be connected to the XOSC. Only one external inductor is required for the VCO. A detailed pin description is given at page 13.
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
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Chipcon
RF Application Circuit Very few external components are required for operation of the RF transceiver. A typical application circuit is shown in Figure 19. Component values are shown in Table 20. Input / output matching C31/L32 is the input match for the receiver, and L32 is also a DC choke for biasing. C41, L41 and C42 are used to match the transmitter to a 50 Ohm load. An internal T/R switch circuit makes it possible to connect the input and output together and match the transceiver to 50 in both RX and TX mode. See the Input / Output Matching section on page 115 for details. VCO inductor The VCO is completely integrated except for the inductor L101. Component values for the matching network and VCO inductor are easily
SmartRF a CC1010
calculated using the SmartRF Studio software for any operation frequency. Additional filtering Additional external components (e.g. RF LC or SAW-filter) may be used in order to improve the performance in specific applications. See also the Optional LC Filter section on page 117 for further information. Voltage supply decoupling Voltage supply filtering and de-coupling capacitors must be used (not shown in the application circuit). These capacitors should be placed as close as possible to the voltage supply pins of CC1010. The placement and size of the decoupling capacitors and power supply filtering are very important to achieve the best sensitivity and lowest possible LO leakage and the reference layouts should be followed.
(R)
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DVDD
SmartRF a CC1010
DVDD
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P0_2 (MISO) AGND DVDD AD2 (RSSI/IF) RESET PROG DVDD AD1 AD0 P2_7 P2_6 P1_7 P1_6 P1_5 P0_3 DGND P3_0 (RXD0) 48 P3_1 (TXD0) 47 P3_2 (INT0) 46 P2_5 45 P2_4 44 DVDD (Top view)
AVDD 1 2 Antenna C31 3 4 5 C42 C41 AVDD L101 L41 L32 6 7 8 9 10 11 12 13 14 15 R131 16 AVDD AVDD AGND RF_IN
RF_OUT AVDD AGND AGND AGND L1 L2 AVDD CHP_OUT R_BIAS AVDD (PWM3) P3_5 (RXD1) P2_0 (TXD1) P2_1 XOSC32_Q2 XOSC32_Q1 AGND XOSC_Q1 XOSC_Q2 AGND (PWM2) P3_4
CC1010
DVDD 43 P2_3 42 DGND 41 DVDD 40 P2_2 39 P1_4 38 P1_3 37 P1_2 36 P1_1 35 P0_1 (MOSI) 34 (INT1) P3_3 DGND P0_0 (SCK) 33
POR_E
DGND
DGND
AGND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
XTAL
C181
C171
Figure 19. Typical CC1010 application circuit
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
P1_0
Page 81 of 133
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SmartRF a CC1010
Table 20. Bill of materials for the application circuit
Item
C31 C41 C42 C171 C181 L32
315 MHz
TBD pF, 5%, C0G, 0603 TBD pF, 5%, C0G, 0603 TBD pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 TBD nH, 10%, 0805
433 MHz
10 pF, 5%, C0G, 0603 6.8 pF, 5%, C0G, 0603 8.2 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 68 nH, 10%, 0805
(Coilcraft 0805CS-680XKBC)
868 MHz
8.2 pF, 5%, C0G, 0603 Not used 10 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 12 nH, 10%, 0805
(Coilcraft 0805CS-120XKBC)
915 MHz
8.2 pF, 5%, C0G, 0603 Not used 10 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 12 nH, 10%, 0805
(Coilcraft 0805CS-120XKBC)
L41
TBD nH, 10%, 0805
6.2 nH, 10%, 0805
(Coilcraft 0805HQ-6N2XKBC)
2.5 nH, 10%, 0805
(Coilcraft 0805HQ-2N5XKBC)
2.5 nH, 10%, 0805
(Coilcraft 0805HQ2N5XKBC)
L101
TBD nH, 5%, 0805
27 nH, 5%, 0805 (Koa KL732ATE27NJ)
3.3 nH, 5%, 0805 (Koa KL732ATE3N3C) 82 k, 1%, 0603 14.7456 MHz crystal, 16 pF load
3.3 nH, 5%, 0805 (Koa KL732ATE3N3C) 82 k, 1%, 0603 14.7456 MHz crystal, 16 pF load
R131 XTAL
82 k, 1%, 0603 14.7456 MHz crystal, 16 pF load
82 k, 1%, 0603 14.7456 MHz crystal, 16 pF load
Note: Shaded items are different for different frequencies Note that the component values for 868 and 915 MHz can be the same. However, it is important that the layout is optimised for the selected VCO inductor in order to centre the tuning range around the operating frequency to account for inductor tolerance. The VCO inductor must be placed very close and symmetrical with respect to the pins (L1 and L2). Chipcon provide reference layouts that should be followed very closely in order to achieve the best performance. The reference design can be downloaded from the Chipcon website.
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SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 82 of 133
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Transceiver Configuration Overview The RF transceiver configuration can be optimised to achieve the best performance for different applications. Through the SFR registers the following key parameters can be programmed: * Receive / transmit mode * RF output power * Frequency synthesiser key parameters: RF output frequency, FSK frequency separation (deviation), crystal oscillator reference frequency * Power-down / power-up mode * Data rate and data format (NRZ, Manchester coded, Transparent or UART interface) * Synthesiser lock indicator mode.
SmartRF a CC1010
* Optional RSSI or external IF output SmartRF Studio Chipcon provides users of CC1010 with a Windows application, SmartRF Studio, which generates all necessary CC1010 RF configuration settings based on the user's selections of various parameters. These SFR register settings can be used in a CC1010 program to configure the RF. In addition SmartRF Studio will provide the user with the component values needed for the input/output matching circuit and the VCO inductor. Figure 20 shows the user interface of SmartRF Studio.
Figure 20. SmartRF Studio
(R)
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Chipcon
SmartRF a CC1010
RF Transceiver RX/TX control and power management
RFMAIN register controls the The operation mode (RX or TX), use of the dual frequency registers and several power down modes. In this way the CC1010 offers great flexibility for RF power management in order to meet strict power consumption requirements in battery operated applications. Different power down modes are controlled through individual bits in the RFMAIN register. There are separate bits to control the RX
RFMAIN (0xC8) - RF Main Control Register
Bit 7
6 5
part, the TX part, the frequency synthesiser and the crystal oscillator. This individual control can be used to optimise for lowest possible current consumption in a certain application. A typical power-on sequence for minimum power consumption is shown in Figure 21. The figure assumes that frequency A is used for RX and frequency B is used for TX. If this is not the case, simply invert the F_REG setting.
Name
RXTX F_REG RX_PD
R/W R/W
R/W R/W
4 3 2 1 0
TX_PD FS_PD CORE_PD BIAS_PD -
R/W R/W R/W R/W R0
Description RX/TX Switch. 0 : RX 1 : TX Select the frequency registers A or B 0 : Select frequency registers A 1 : Select frequency registers B Select power down for the LNA, mixer, IF filter and digital demodulator. 0 : Power up 1 : Power down Select power down of the digital modem and PA. 0 : Power up 1 : Power down Select power down of the frequency synthesizer 0 : Power up 1 : Power down Power down of main crystal oscillator core. 0 : Power up 1 : Power down Power down of bias current generator and crystal oscillator buffer. 0 : Power up 1 : Power down Reserved, read as 0
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SmartRF a CC1010
RF Power Down
RX
RX or TX?
TX
Turn on RX: RFMAIN: RXTX = 0, F_REG = 0 RX_PD = 0, FS_PD = 0 CURRENT = `RX current' Wait 250 s
Turn on TX: PA_POW = 00h RFMAIN: RXTX = 1, F_REG = 1 TX_PD = 0, FS_PD = 0 CURRENT = `TX current' Wait 250 s PA_POW = `Output power' Wait 20 s
RX mode
Turn off RX: RFMAIN: RX_PD = 1, FS_PD = 1
TX mode
RF Power Down
Turn off TX: RFMAIN: TX_PD = 1, FS_PD = 1 PA_POW = 00h
RF Power Down
Figure 21. RF Transceiver power-on sequence
Chipcon AS
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Chipcon
Data Modem and Data Modes Four different data modes are defined for transmission and reception, programmable through MODEM0.DATA_FORMAT. These modes differ in data encoding, how incoming and outgoing data is delivered and accepted, and whether resynchronisation of the bitstream is performed (clock regeneration) or not. The data format should be selected before enabling the RF Transceiver Two of the modes, Synchronous NRZ mode and Synchronous Manchester encoded mode, transmit or receive data using a baudrate as specified in MODEM0.BAUDRATE. The modem does resynchronisation of the bit stream during reception. In the Manchester mode the modem also does the Manchester encoding and decoding. The NRZ and Manchester modes accept and deliver data either one bit or one byte at a time, programmable through RFCON.BYTEMODE. In most applications these two modes are recommended. Data to be transmitted or data received are stored in the RFBUF register. During transmission or reception the need for more data or the arrival of new data, bit by bit or byte by byte depending on RFCON.BYTEMODE, is signaled by generating an interrupt (EXIF.RFIF.) Depending on whether the RF interrupt is enabled or not (EIE.RFIE), transmission or reception can be handled by an interrupt service routine or be performed by polling. During reception when using NRZ or Manchester mode, hardware preamble
SmartRF a CC1010
and start of frame detection can optionally be activated using the registers PDET and BSYNC. This is described in the Synchronization and preamble detection section on page 96. Two other modes, Transparent mode and UART mode, simply passes data between the FSK modem and the RFBUF register and UART0, respectively, allowing custom baud rates and data encoding. When using the UART0 in the UART mode the pin P3.1 is not used for UART output and can instead be used for general I/O. Manchester encoding In Manchester mode the data clock is transmitted along with the data. A '1' is encoded as a high frequency f1 followed by a lower frequency f0. A '0' is encoded as a low frequency f0 followed by a higher frequency f1. This is illustrated in Figure 22. See the Frequency programming section on page 100 for definitions of f0 and f1. The Manchester code ensures that the signal has a constant DC component, which is necessary in some FSK demodulators. Using this mode also ensures compatibility with CC400 / CC900 designs. The properties of the different data modes are summarized in Table 21.
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SmartRF a CC1010
10110001101
TX data
f1 f0
Time
Figure 22. Manchester encoding Table 21. Properties of different data modes (MODEM0.DATA_FORMAT)
Transparent mode Baudrate configuration Data encoding
User defined User defined
UART mode
Defined by UART through Timer 1 Defined by UART settings N/A
Synchronous Synchronous NRZ Manchester mode encoded mode Generated by hardware, as defined by
MODEM0.BAUDRATE
Manchester None (NRZ) encoding. Bitrate is half of baudrate. RFBUF in bytemode, RFBUF(0) in bitmode.
Data Input & Output
RFBUF(0)
N/A
Clock Regeneration
Performed by UART
Performed internally. A violation to the Manchester coding format is reported in RFCON.MVIOL.
Performed by hardware
Bitmode/ Bytemode Preamble detection
N/A N/A
N/A N/A
Both possible. Bytemode is forced when using preamble detection If PDET.PEN=1 a configurable number of alternating '0's and '1's (PDET.PLEN) followed by a one-byte start of frame delimiter as defined in BSYNC is needed to trigger reception. Bytemode is forced when PDET.PEN=1.
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MODEM0 (0xDB) - Modem Control Register 0
Bit 7:5 Name
SmartRF a CC1010
BAUDRATE (2:0)
R/W R/W
4:3
DATA_FORMAT (1:0) XOSC_FREQ (2:0)
R/W
2:0
R/W
Description 000 : 0.6 kBaud 001 : 1.2 kBaud 010 : 2.4 kBaud 011 : 4.8 kBaud 100 : 9.6 kBaud 101 : 19.2, 38.4 and 76.8 kBaud 110 : Not used 111 : Not used 00 : NRZ mode 01 : Manchester mode 10 : Transparent mode 11 : UART mode Select the current crystal oscillator frequency. 000 : 3-4 MHz, 3.6864 MHz recommended Also used for 76.8 kBaud for 14.7456 MHz and 38.4 kBaud for 7.3728 MHz 001 : 6-8 MHz, 7.3728 MHz recommended Also used for 38.4 kBaud for 14.7456 MHz 010 : 9-12 MHz, 11.0592 MHz recommended Also used for 38.4 kBaud for 22.1184 MHz 011 : 12-16 MHz, 14.7456 MHz recommended 100 : 16-20 MHz, 18.4320 MHz recommended 101 : 20-24 MHz, 22.1184 MHz recommended 110 : Reserved for future use 111 : Reserved for future use
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Page 88 of 133
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Baudrates Baudrates from 0.6 kBaud to 76.8 kBaud are programmable in the MODEM0.BAUDRATE control bits. MODEM0.XOSC_FREQ must also be set
SmartRF a CC1010
according to the crystal in use. Baudrates are generated as follows:
RF _ BAUDRATE =
f xosc 2 BAUDRATE 0.6 kBaud ( XOSC _ FREQ + 1) 3.6864 MHz
Other crystal frequencies will scale the baudrate as described above. Baudrates up to and including 19.2 kBaud can be generated for any crystal frequency. Above 19.2 kBaud a few combinations are possible, as shown in Table 22.
RF_BAUDRATE is the output baudrate in kBaud, BAUDRATE and XOSC_FREQ are control bits in MODEM0. Using one of the standard crystals mentioned in the MODEM0.XOSC_FREQ description will produce the standard baudrates 0.6, 1.2, 2.4, 4.8, 9.6, 19.2, 38.4 or 76.8 kBaud.
Table 22. Baudrates versus crystal frequency
MODEM0. BAUDRATE /XOSC.FREQ
RF_BAUDRATE [kBaud] 0.6 1.2 2.4 4.8 9.6 19.2 38.4 76.8 3.6864
0/0 1/0 2/0 3/0 4/0 5/0 NA NA
f_xosc [MHz] 7.3728
0/1 1/1 2/1 3/1 4/1 5/1 5/0 NA
11.0592
0/2 1/2 2/2 3/2 4/2 5/2 NA NA
14.7456
0/3 1/3 2/3 3/3 4/3 5/3 5/1 5/0
18.4320
0/4 1/4 2/4 3/4 4/4 5/4 NA NA
22.1184
0/5 1/5 2/5 3/5 4/5 5/5 5/2 NA
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Transmitting and receiving data In the Transparent or UART modes outgoing and incoming data is routed directly to the modulator in transmit mode and directly from the demodulator in receive mode. In the NRZ and Manchester
RF Transmitter Modulator
SmartRF a CC1010
modes, however, data buffering occurs in RFBUF as illustrated in Figure 23. This buffering has some repercussions that must be considered when receiving or transmitting data, particularly in bytemode.
RF Receiver Demodulator
8-bit shift reg.
RFBUF
LSB
8051 core
Figure 23. RF Data Buffering. Dotted lines show bitmode RFBUF (0xC9) - RF Data Buffer
Bit 7:0 Name
RFBUF
R/W R/W
Description RF Data Buffer, 8 bits. RFBUF is used as described below.
Transmission When transmitting data in bytemode (RFCON.BYTEMODE=1), the buffering scheme shifts out bits of an 8 bit shift register to the modulator one at a time, MSB first, at periods specified by the selected baudrate. When this shift register is empty it will load a new byte from RFBUF and continue shifting out bits. The contents of the RFBUF register remain intact after a shift register load, however, an interrupt request is generated (EICON.RFI) so that RFBUF can be loaded with a new data byte. If a new byte is not written within eight bit periods (eight baud periods in NRZ mode and 16 baud periods in Manchester mode), the next time the shift register is empty it will load the same byte from
RFBUF again. E.g. when transmitting a preamble consisting of alternating '0' and '1', it is only necessary to write the byte to RFBUF once and then wait the desired number of byte cycles for the preamble to be transmitted.
In bitmode (RFCON.BYTEMODE=0), the same buffering occurs, but only for one bit at a time. Thus, the shift register will load a new bit from RFBUF.0 after each transmitted bit, which in turn generates a RF-interrupt request so that a new bit can be loaded. In order to be able to write the next bit to RFBUF.0 within one bit period at high baud rates, it is advisable to use a tight polling loop instead of an interrupt based transmit procedure. In order to start transmission of data as quickly as possible, the first bit/byte to be
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transmitted should be written to RFBUF before the modulator is turned on (RFMAIN.TX_PD=0). It will then be immediately loaded into the shift register and an interrupt request will be generated for the second bit/byte. It is especially important to take the buffering scheme into account at the end of a transmission. When the last byte of a data frame or packet is loaded into the shift register it is still not transmitted. Thus the interrupt request generated at the same time must not lead to the turning off of either analog or digital parts of the transmit chain. The transmission can not be ended safely until nine bit periods later in bytemode and two bit periods later in bitmode, when the last bit has been shifted out and has propagated through the transmit chain to the antenna. A simple solution is to always transmit two extra bytes in bytemode or two extra bits in bitmode at the end of the real data content. (In bytemode this will result in that approximately seven of these bits will be transmitted along with the real data.)
SmartRF a CC1010
Reception When receiving data the buffering scheme works in reverse of what it does during transmitting. Bit by bit from the demodulator is shifted into the eight-bit shift register, MSB-first: When the shift register is full it is loaded into RFBUF and an interrupt request is generated (EICON.RFIF). The byte must be read within one byte period (eight baud periods in NRZ mode and 16 baud periods in Manchester mode). If not, it will be overwritten by the next byte received and data is lost. In bitmode the same buffering occurs, but only for one bit at a time. Thus, when a new bit arrives from the demodulator the shift register will store it and store the last bit into RFBUF.0, which in turn generates a RF-interrupt request so that the new bit can be read. In order to be able to read the next bit from RFBUF.0 within one bit period at high baud rates it is advisable to use a tight polling loop instead of an interrupt based receive procedure. No special considerations have to be taken at the start of, or end of, receptions.
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Demodulation and data decision A block diagram of the digital demodulator is shown in Figure 24. The IF signal is sampled and it's instantaneous frequency is detected. The result is decimated and filtered. In the data slicer the data filter output is compared to the average filter output to generate the data output. The averaging filter is used to find the average value of the incoming data. While the averaging filter is running and acquiring samples, it is important that the number of high and low bits received is equal (e.g. Manchester code or a balanced preamble). Therefore all modes, also synchronous NRZ mode, need a DC balanced preamble for the internal data slicer to acquire correct comparison level from the averaging filter. The suggested preamble is a `010101...' bit pattern. The same bit pattern should also be used in Manchester mode, giving a `011001100110...`chip' pattern. This is necessary for the bit synchronizer to synchronize correctly. The averaging filter must be locked before any NRZ data can be received. This can be done in one of two ways: * After receiving the preamble and byte synchronisation (see the Synchronization and preamble detection section on page 96), set MODEM1.LOCK_AVG_IN='1' to stop updating the averaging filter. Set MODEM1.LOCK_AVG_MODE='1', and then enter Receive mode (RFMAIN.RX_PD='0'). The averaging filter will then be automatically locked after a preset number of baud periods, programmable in MODEM1.SETTLING. The settling time is programmable from 11 to 86 bauds. The average filter lock status can be read through MODEM1.AVG_FILTER_STAT.
SmartRF a CC1010
After a modem reset (MODEM1.MODEM_RESET_N), or a main reset (RFMAIN.RESET_N), the averaging filter is reset. In a polled receiver system the automatic locking can be used. This is illustrated in Figure 25. If the receiver is operated continuously and searching for a preamble, the averaging filter should be locked manually as soon as the preamble is detected. This is shown in Figure 26. If the data is Manchester coded there is no need to lock the averaging filter (MODEM1.LOCK_AVG_IN='0'), as shown in Figure 27. The minimum length of the preamble depends on the acquisition mode selected and the settling time. Table 23 gives the minimum recommended number of chips for the preamble in NRZ and UART modes. In this context `chips' refer to the data coding. Using Manchester coding every bit consists of two `chips'. For Manchester mode the minimum recommended number of chips is shown in Table 24. A special feature in the data filter is a peak remover acting like a low pass filter. The peak threshold must be programmed according to the deviation and expected frequency drift. When MODEM1.PEAKDETECT is enabled, MODEM2.PLO should be set such that:
*
PLO =
where
fS fs - IFlow IF + f low
2
5 8
fs =
f XOSC MODEM 0. XOSC _ FREQ + 1
IFlow = 150kHz - 2 f RF XTAL _ accuracy
and f is the deviation. SmartRF Studio may be used to configure this correctly.
(R)
If the averaging filter is locked (MODEM1.LOCK_AVG_MODE='1'), the acquired value will be kept also after Power Down or Transmit mode.
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SmartRF a CC1010
Average filter
Sampler
Frequency detector
Decimator
Data filter
Data slicer comparator
Figure 24. Demodulator block diagram
Data package to be received Noise RX PD Averaging filter free-running / not used Preamble RX Averaging filter locked NRZ data Noise
Automatically locked after a short period depending on "SETTLING"
Figure 25. Automatic locking of the averaging filter
Data package to be received Noise PD RX Averaging filter locked Preamble NRZ data Noise
Averaging filter free-running
Manually locked after preamble is detected
Figure 26. Manual locking of the averaging filter
Data package to be received Noise PD RX Preamble Manchester encoded data Noise
Averaging filter always free-running
Figure 27. Free-running averaging filter
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SmartRF a CC1010
Table 23. Minimum number of bits in the preamble, NRZ and UART mode
Settling NRZ mode Manual Lock UART mode NRZ mode Automatic Lock UART mode
MODEM1. SETTLING (1:0)
00 01 10 11
MODEM1.LOCK_ AVG_MODE='1' MODEM1.LOCK_ AVG_IN='0'='1'**
14 25 46 89
MODEM1.LOCK_ AVG_MODE='1' MODEM1.LOCK_ AVG_IN='0'='1'**
11 22 43 86
MODEM1.LOCK_ AVG_MODE='0' MODEM1.LOCK_ AVG_IN='X'***
16 32 64 128
MODEM1.LOCK_ AVG_MODE='0' MODEM1.LOCK_ AVG_IN='X'***
16 32 64 128
Notes: ** The averaging filter is locked when MODEM1.LOCK_AVG_IN is set to 1 *** X = Do not care. The timer for the automatic lock is started when RX mode is set in the RFMAIN register
Table 24. Minimum number of chips in the preamble, Manchester mode
Settling Free-running Manchester mode
MODEM1. SETTLING (1:0)
00 01 10 11
MODEM1.LOCK_ AVG_MODE='1' MODEM1.LOCK_ AVG_IN='0'
23 34 55 98
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MODEM1 (0xDA) - Modem Control Register 1
Bit 7 6 Name
SmartRF a CC1010
LOCK_AVG_IN
R/W R0 R/W
5
LOCK_AVG_MODE
R/W
4 3:2
LOCK_AVG_STAT SETTLING(1:0)
R R/W
1 0
PEAKDETECT MODEM_RESET_N
R/W R/W
Description Reserved, read as 0 Lock control bit of average filter 0 : Average Filter is free-running, used for receiving zero average data (e.g. Preamble or Manchester encoded data) 1 : Lock average filter, used for NRZ data Automatic lock of average filter 0 : Lock of Average Filter is controlled automatically, use when zero average data is present when the receiver is turned on 1 : Lock of Average Filter is controlled by LOCK_AVG_IN Average filter status bit 0 : Average filter is free running 1 : Average filter is locked Settling time of average filter 00 : 11 baud settling time, worst case 1.2dB loss in sensitivity 01 : 22 baud settling time, worst case 0.6dB loss in sensitivity 10 : 43 baud settling time, worst case 0.3dB loss in sensitivity 11 : 86 baud settling time, worst case 0.15dB loss in sensitivity Peak detector and remover enable / disable 0 : Peak detector and remover is disabled. 1 : Peak detector and remover is enabled Separate reset of the MODEM. 0 : The Modem is reset 1 : The Modem reset is released
MODEM2 (0xD9) - Modem Control Register 2
Bit 7 6:0 Name
PLO(6:0)
R/W R0 R/W
Description Reserved, read as 0 Peak Level Offset, threshold level for peak the peak detector and remover in the demodulator, which is activated when MODEM1.PEAKDETECT is set. PLO should be set as described on page 92.
RFCON (0xC2) - RF Control Register
Bit 7:5 4 Name
MVIOL
R/W R0 R
3:1
MLIMIT(2:0)
R/W
0
BYTEMODE
R/W
Description Reserved, read as 0 Manchester code violation status of current bit in bitmode or the aggregate-OR of the Manchester code status of all bits in the current byte in bytemode. Only valid when MODEM0.DATA_FORMAT=01 (Manchester encoding) Limit value used by the clock regeneration logic in Manchester mode to determine whether the current symbol constitutes a Manchester code violation. The violation detection is determined by how balanced the bit is by looking at the 14 samples. A perfect bit is 14 (all samples are correct). The limit can be set from 1 to 7 (001 - 111). 0 disable the violation detection function. Select bit or bytemode 0 : Bitmode is enabled. Data is transmitted and received bit by bit through RFBUF.0 1 : Bytemode is enabled. Data is transmitted and received byte by byte through RFBUF, with MSB first. BYTEMODE is ignored if PDET.PEN = 1
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Synchronization and preamble detection Most RF communication protocols will have a preamble designated to let the receiver synchronise its reception on a bit and byte level. CC1010 contains hardware that will perform these tasks easily in synchronous NRZ and Manchester encoded modes. The byte synchronization mechanism ensures that the framing of bytes in the received data bit stream is correct, thus freeing the software from needing to perform shifting and recombination of data bytes. In addition, the synchronization byte functions as a start of frame delimiter. The preamble detection mechanism reduces the workload for the processor when the exact time of the start of a transmission is uncertain. Both mechanisms are active when PDET.PEN is set. (See PDET
SmartRF a CC1010
register definition below.) Two preamble examples are shown in Figure 28. Note that the Manchester baudrate is twice the NRZ baudrate in the figure. The preamble must consist of an alternating 0-1-pattern followed by a synchronization byte of any eight bits. Unless the average filter is already locked at the arrival of the synchronization byte in NRZ mode, it is vital that the synchronization byte is DC-balanced (equal number of zeros and ones) and contains no more than two consecutive ones or zeros. It is also required that the synchronization byte contains two consecutive ones or zeros. This means that e.g. 0xCC is not a legal synchronization byte, but 0xC5 is.
NRZ Bit value 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 1 0 0 1 0
Manchester Bit value 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 1 0 0 1 0
Preamble
Byte sync
Data
Figure 28. Preamble detection examples PDET (0xD3) - Preamble Detection Control Register
Bit 7 Name
PEN
R/W R/W
6:0
PLEN
R/W
Description Preamble and byte synchronisation enable. 0 : Receiver mode is defined by RFCON.BYTEMODE. 1 : Preamble and byte synchronisation is enabled. RFCON.BYTEMODE is don't care. Preamble length. Define the number of alternating bits required before byte synchronisation. PLEN must be greater than zero.
BSYNC (0xD4) - Byte Synchronisation Register
Bit 7:0 Name
BSYNC(7:0)
R/W R/W
Description BSYNC defines the byte which triggers byte synchronisation during RF preamble detection.
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The hardware support for preamble detection consists of a seven bit counter, which keeps track of the number of successive alternating bits. It is reset whenever two bits are equal and incremented whenever two successive bits are different. The counter is limited and will not overflow. A seven-bit threshold is programmable through PDET.PLEN. Not before this counter equals or exceeds PDET.PLEN will a synchronization byte be accepted. CC1010 is able to detect preambles (including the synchronization byte) with minimum lengths from 10 to 135 bits. When the requisite number of alternating zeros and ones has been received, a special state is entered in which a break in the 0-1-pattern is searched for. Once such a break occurs, a synchronization byte matching that defined in BSYNC must occur within a maximum of seven bits, otherwise the receiver will reset its preamble counter and go back to the preamble detection mode. If, however, a match is found before the timeout, the synchronization byte is transferred to RFBUF and an EXIF.RFIF interrupt request generated, after which the receiver enters normal reception mode. For both the examples shown in Figure 28, BSYNC should be set to 10100101.
SmartRF a CC1010
Manchester Violations In some RF-applications using Manchester coding, violations of the Manchester coding have been used for start- and endof-frame delimiters. Furthermore some implementations use a sequence of all ones or all zeros for a preamble instead of an alternating zero-one sequence. Although an all zero or all one sequence will certainly be DC-balanced once Manchester coded, the receiver is unable to decide whether it is receiving an all zero or an all one sequence, since only the bit synchronization will separate these. In order to facilitate reception and transmission of such special cases, support has been implemented in CC1010 for allowing the data format to be changed in the middle of a reception or transmission. Furthermore, violations to the Manchester coding format is reported in the status bit RFCON.MVIOL. The threshold for determining what constitutes a Manchester coding violation can be configured in RFCON.MLIMIT. RFCON.MVIOL is set when, in bitmode, the currently available bit in RFBUF.0 was determined to violate Manchester coding, or in bytemode, when one or more of the bits in the byte currently available in RFBUF were determined to violate the Manchester coding. This can be used, for example, to detect start of frame and end of frame delimiter bytes. Note that even if RFCON.MVIOL is set when receiving data, RFBUF will still be set to the "best guess" data received. In applications where no Manchester violations are transmitted, it is therefore advisable to ignore RFCON.MVIOL at reception. In order to be able to send Manchester violations, MODEM0.DATA_FORMAT must be changed to NRZ mode for the byte in question. When in NRZ mode, two bytes must be sent for each Manchester-coded byte. A flagrant violation of Manchester coding could be, for example, the two-byte sequence "11001100"-"00110011". In order to provide this functionality, MODEM0.DATA_FORMAT is buffered in
PDET.PEN is not cleared by hardware when the preamble is detected, but it will not affect the reception of data. It can be cleared or left set, decided by what is more practical for the software developer. However, before a new preamble detection is initiated, PDET.PEN must be cleared.
If manual average filter locking is performed, the average filter should be locked after receiving the synchronization byte in NRZ mode. (See the Reception section on page 91 for details.) As mentioned above it is vital that the synchronization byte is DC-balanced and contains no more than two consecutive ones or zeros in order to achieve a good average filter lock in this case.
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much the same way as data so that the change does not take effect until the following byte. During transmission, the desired data format should be updated in connection with writing new data to RFBUF. The byte
NRZ Preamble
SmartRF a CC1010
currently being transmitted from the shift register will not be affected. It is then possible to have a NRZ preamble pattern with Manchester data following. This is illustrated in Figure 29.
Manchester data
Bit value
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
0
Preamble
Byte sync
Data
Figure 29. Switching data mode after preamble Changing the desired data mode during reception of NRZ preamble and Manchester data is straightforward. A new value of MODEM0.DATA_FORMAT does not take effect before an RF interrupt request is generated. After having started a reception using preamble detection/byte synchronization and the NRZ data mode, the DATA_FORMAT should be set to Manchester. The whole preamble detection process will then work with NRZ data and the new DATA_FORMAT will not take effect until a valid (NRZ) synchronization byte is found and an interrupt request generated. It is not recommended to change the data format during reception for new protocols, but the functionality is included for compatibility with existing protocols.
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SmartRF a CC1010
Receiver sensitivity versus data rate and frequency separation The receiver sensitivity depends on the data rate, the data format, FSK frequency separation and the RF frequency. Typical figures for the receiver sensitivity (BER = -3 10 ) are shown in Table 25 for 64 kHz frequency separations and for 20 kHz. Optimised sensitivity configurations are used. For best performance the frequency separation should be as high as possible especially at high data rates.
-3
Table 25. Receiver sensitivity as a function of data rate at 433 and 868 MHz, BER = 10 , frequency separation 64 kHz
Data rate [kBaud] Separation [kHz] 433 MHz NRZ mode TBD TBD TBD TBD TBD TBD TBD TBD Manchester mode -110 -109 -107 -105 -103 -102 -100 -100 UART mode TBD TBD TBD TBD TBD TBD TBD TBD 868 MHz NRZ mode TBD TBD TBD TBD TBD TBD TBD TBD Manchester mode -110 -108 -106 -103 -102 -101 -99 -99 UART mode TBD TBD TBD TBD TBD TBD TBD TBD
0.6 1.2 2.4 4.8 9.6 19.2 38.4 76.8
64 64 64 64 64 64 64 64
Table 26. Receiver sensitivity as a function of data rate at 433 and 868 MHz, BER = 10 , frequency separation 20 kHz
Data rate [kBaud] Separation [kHz] 433 MHz NRZ mode TBD TBD TBD TBD TBD TBD TBD TBD Manchester mode TBD TBD TBD TBD TBD TBD TBD TBD UART mode TBD TBD TBD TBD TBD TBD TBD TBD 868 MHz NRZ mode TBD TBD TBD TBD TBD TBD TBD TBD Manchester mode TBD TBD TBD TBD TBD TBD TBD TBD UART mode TBD TBD TBD TBD TBD TBD TBD TBD
-3
0.6 1.2 2.4 4.8 9.6 19.2 38.4 76.8
20 20 20 20 20 20 20 20
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Frequency programming The frequency synthesiser (PLL) is controlled by the frequency word in the configuration registers. There are two frequency words, A and B, which can be programmed to two different frequencies. One of the frequency words can be used for RX (local oscillator frequency) and other for TX (transmitting frequency, f0). This makes it possible to switch very fast between RX mode and TX mode. They can also be used for RX (or TX) at two different channels. Frequency word A or B is selected by the RFMAIN.F_REG control bit. The frequency word, FREQ, is 24 bits (3 bytes) located in FREQ_2A:FREQ_1A:FREQ_0A and FREQ_2B:FREQ_1B:FREQ_0B for the A and B word, respectively. The FSK frequency separation (two times the deviation), FSEP, is programmed in the FSEP1:FSEP0 registers (11 bits). The frequency calculated from: word FREQ can be
SmartRF a CC1010
Thus, the reference frequency fref is:
f ref =
f xosc REFDIV
fVCO is the Local Oscillator (LO) frequency for receive mode, and the f0 frequency for transmit mode (lower FSK frequency). The LO frequency must be fRF - fIF or fRF + fIF giving a low-side or high side LO injection respectively. Note that the data in RFBUF will be inverted if high-side LO is used. Do also note that the fIF depend on the RF frequency (150 and 130 kHz for 433 and 868 MHz respectively). The upper FSK transmit frequency is given by: f1 = f0 + fsep where the frequency separation fsep is set by the 11 bit separation word (FSEP1:FSEP0):
f sep = f ref
FSEP 16384
f VCO = f ref
FREQ + FSEP TXDATA + 8192 16384
where TXDATA is 0 or 1 in transmit mode depending on the data bit to be transmitted. In receive mode TXDATA is always 0. The reference frequency fref is the crystal oscillator clock divided by PLL.REFDIV, a number between 2 and 24 such that: 1.00 MHz REFDIV 2.40 MHz
PLL.ALARM_DISABLE will Clearing enable generation of the frequency alarm bits PLL.ALARM_H and PLL.ALARM_L. These bits indicate that the frequency synthesis PLL is unable to generate the frequency requested, and the PLL should be recalibrated as described in the VCO and PLL self-calibration section on page 105.
Chipcon recommends using the frequency settings described in the Recommended Settings for ISM Frequencies section on page 103.
FREQ_2A (0xCC) - Frequency A, Control Register 2
Bit 7:0 Name
FREQ_A (23:16)
R/W R/W
Description 8 MSB of frequency control word A. It must be programmed such that FREQ_2A 01000000
FREQ_1A (0xCB) - Frequency A, Control Register 1
Bit 7:0 Name
FREQ_A (15:8)
R/W R/W
Description Bit 15 to 8 of frequency control word A.
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SmartRF a CC1010
FREQ_0A (0xCA) - Frequency A, Control Register 0
Bit 7:0 Name
FREQ_A(7:0)
R/W R/W
Description 8 LSB of frequency control word A.
FREQ_2B (0xCF) - Frequency B, Control Register 2
Bit 7:0 Name
FREQ_B (23:16)
R/W R/W
Description 8 MSB of frequency control word B. It must be programmed such that FREQ_2B 01000000
FREQ_1B (0xCE) - Frequency B, Control Register 1
Bit 7:0 Name
FREQ_B (15:8)
R/W R/W
Description Bit 15 to 8 of frequency control word B.
FREQ_0B (0xCD) - Frequency B, Control Register 0
Bit 7:0 Name
FREQ_B(7:0)
R/W R/W
Description 8 LSB of frequency control word B.
FSEP1 (0xEB) - Frequency Separation Control Register 1
Bit 7:3 2:0 Name
FSEP(10:8)
R/W R0 R/W
Description Reserved, read as 0 3 MSB of the frequency separation control word FSEP
FSEP0 (0xEA) - Frequency Separation Control Register 0
Bit 7:0 Name
FSEP(7:0)
R/W R/W
Description 8 LSB of the frequency separation control word FSEP
PLL (0xE3) - PLL Control Register
Bit 7:3 Name
REFDIV(4:0)
R/W R/W
2
ALARM_ DISABLE ALARM_H ALARM_L
R/W
1 0
R R
Description Reference divider setting. The main crystal oscillator frequency is divided by REFDIV to create the RF reference frequency fref. Valid REFDIV settings are 2 through 24, as described above. Disable / Enable the generation of the ALARM_H and ALARM_L bits 0 : Alarm function enabled 1 : Alarm function disabled Status bit for tuning voltage out of range (too close to VDD) The PLL should be re-calibrated if this bit is set Status bit for tuning voltage out of range (too close to GND) The PLL should be re-calibrated if this bit is set
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Lock Indication The frequency synthesis PLL has a lock indicator which can be read from the LOCK register. LOCK_INSTANT is a single sample of the phase difference between the reference frequency and the divided VCO frequency. This bit gives a lock accuracy of > 25 %, depending on the division ratio set by the FREQ registers. To be used as a lock indicator, this bit must be sampled over a period of time to increase the accuracy. LOCK (0xE4) - PLL Lock Register
Bit 7:4 3 Name
SmartRF a CC1010
Otherwise LOCK_CONTINUOUS should be used. It is a filtered version of LOCK_INSTANT, giving a lock accuracy of 99.3 % with PLL_LOCK_ACCURACY cleared. If lock is not achieved, the PLL should be recalibrated as described on page 105.
PLL_LOCK_ACCURACY
R/W R0 R/W
2 1 0
PLL_LOCK_LENGTH LOCK_INSTANT LOCK_CONTINUOUS
R/W R R
Description Reserved, read as 0 0 : Sets Lock Threshold = 127, Reset Lock Threshold = 111 for continuous lock. Corresponds to a worst case accuracy of 99.3% 1 : Sets Lock Threshold = 31, Reset Lock Threshold =15 for continuous lock. Corresponds to a worst case accuracy of 97.2% 0 : Normal PLL lock window 1 : Not used Status bit from Lock Detector. The result of one sample of the lock window on the PLL reference clock Status bit from Lock Detector, set according to the PLL_LOCK_ACCURACY setting
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Recommended Settings for ISM Frequencies The recommended frequency synthesiser settings for a few operating frequencies in the popular ISM bands are shown in Table 27. These settings ensure optimum configuration of the synthesiser in receive mode for best sensitivity. For some settings of the synthesiser (combinations of RF frequencies and reference frequency), the receiver sensitivity is degraded. The performance of the
ISM Frequency [MHz]
315
SmartRF a CC1010
transmitter is not affected by the settings, but recommended transmitter settings are included for completeness. The FSK frequency separation is set to 64 kHz. The SmartRF Studio can be used to generate the optimised configuration data as well. Also an application note (AN011) and a spreadsheet are available from Chipcon generating configuration data for any frequency giving optimum sensitivity.
Reference divider REFDIV [decimal]
3 6 9 12 15 18 3 6 9 12 15 18 3 6 9 12 15 18 3 6 9 12 15 18 3 6 9 12 15 18 3 6 9 12 15 18
Actual frequency [MHz]
315.337200
Crystal frequency [MHz]
3.6864 7.3728 11.0592 14.7456 18.4320 22.1184 3.6864 7.3728 11.0592 14.7456 18.4320 22.1184 3.6864 7.3728 11.0592 14.7456 18.4320 22.1184 3.6864 7.3728 11.0592 14.7456 18.4320 22.1184 3.6864 7.3728 11.0592 14.7456 18.4320 22.1184 3.6864 7.3728 11.0592 14.7456 18.4320 22.1184
Low-side / highside LO*
Low-side
Frequency word RX Mode FREQ [decimal]
4194304 4194304 4194304 4194304 4194304 4194304 5767168 5767168 5767168 5767168 5767168 5767168 5775360 5775360 5775360 5775360 5775360 5775360 5783552 5783552 5783552 5783552 5783552 5783552 7708672 7708672 7708672 7708672 7708672 7708672 7716864 7716864 7716864 7716864 7716864 7716864
Frequency word RX mode FREQ [hex]
400000 400000 400000 400000 400000 400000 580000 580000 580000 580000 580000 580000 582000 582000 582000 582000 582000 582000 584000 584000 584000 584000 584000 584000 75A000 75A000 75A000 75A000 75A000 75A000 75C000 75C000 75C000 75C000 75C000 75C000
433.3
433.302000
Low-side
433.9
433.916400
Low-side
434.5
434.530800
Low-side
868.3
868.277200
Low-side
868.95
868.938800
High-side
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ISM Frequency [MHz]
869.525
SmartRF a CC1010
Low-side / highside LO*
Low-side
Actual frequency [MHz]
869.506000
Crystal frequency [MHz]
3.6864 7.3728 11.0592 14.7456 18.4320 22.1184 3.6864 7.3728 11.0592 14.7456 18.4320 22.1184 3.6864 7.3728 11.0592 14.7456 18.4320 22.1184
Reference divider REFDIV [decimal]
3 6 9 12 15 18 3 6 9 12 15 18 3 6 9 12 15 18
Frequency word RX Mode FREQ [decimal]
11583488 11583488 11583488 11583488 11583488 11583488 7725056 7725056 7725056 7725056 7725056 7725056 8126464 8126464 8126464 8126464 8126464 8126464
Frequency word RX mode FREQ [hex]
B0C000 B0C000 B0C000 B0C000 B0C000 B0C000 75E000 75E000 75E000 75E000 75E000 75E000 7C0000 7C0000 7C0000 7C0000 7C0000 7C0000
869.85
869.860400
High-side
915
915.018800
High-side
*Note: When using high-side LO injection the data received in RFBUF will be inverted. Table 27. Recommended settings for ISM frequencies
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VCO Only one external inductor (L101) is required for the VCO. The inductor will determine the operating frequency range of the circuit. It is important to place the inductor as close to the pins as possible in order to reduce stray inductance. It is recommended to use a high Q, low tolerance inductor for best performance. VCO and PLL self-calibration To compensate for supply voltage, temperature and process variations the VCO and PLL must be calibrated. The calibration is done automatically and sets optimum VCO tuning range and optimum charge pump current for PLL stability. The calibration is controlled by using the CAL register. After setting up the device at the operating frequency, the TEST6 register must be programmed (depend on operation mode). Then the self-calibration is initiated by setting the CAL.CAL_START bit. The calibration result is stored internally in the chip, and is valid as long as power is not turned off. If large supply voltage variations (more than 0.5 V) or temperature variations (more than 40 degrees) occur after calibration, a new calibration should be performed. For more details on the calibration data, see the description for test and calibration registers page 118. When CAL.CAL_WAIT = 1 the calibration is complete and the CAL.CAL_COMPLETE flag is set after 25650 reference clock see the Frequency cycles (fREF, programming section at page 100). The user can poll this bit, or simply wait 25650 reference clock cycles. The lowest permitted reference frequency (1 MHz) gives a wait time of 25.65 ms, which is the worst case. Some calibration times for different reference frequencies are listed in Table 28. When CAL.CAL_WAIT = 0 it takes 12825 cycles, but this is not recommended.
SmartRF a CC1010
Typical tuning range for the integrated varactor is 20-25%. Component values for various frequencies are given in Table 20. Component values for other frequencies can be found using (R) the SmartRF Studio software.
Table 28. Calibration times
Reference frequency [MHz] Calibration time [ms]
2.4 2.0 1.5 1.0
10.69 12.83 17.10 25.65
The CAL_START bit must be cleared after the calibration is done. This will also clear the CAL.CAL_COMPLETE status bit. There are separate calibration values for the two frequency registers. If the two frequencies, A and B, differ more than 1 MHz, or different VCO currents are used (CURRENT.VCO_CURRENT(3:0)), the calibration should be done separately. When using a 10.7 MHz external IF the LO is 10.7 MHz below/above the transmit frequency, hence separate calibration must be done. The CAL.CAL_DUAL bit controls dual or separate calibration. The single frequency calibration algorithm using separate calibration for RX and TX frequency is illustrated in Figure 30. In Figure 31 the dual calibration algorithm is shown for two RX frequencies. It could also be used for two TX frequencies, or even for one RX and one TX frequency if the same VCO current is used. In multi-channel and frequency hopping applications the PLL calibration values may be read and stored for later use. By reading back calibration values and frequency change can be done without
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doing a re-calibration which could take up to 25 ms. After a calibration is completed, the result of the calibration is stored in the TEST0 (VCO capacitance array setting) and TEST2 (Charge pump current setting) registers. The access of these registers depend on the RFMAIN.F_REG bit as there are two physical registers mapped to the same address, one for frequency A and one for frequency B. The calibration result can be read back from TEST0 and
SmartRF a CC1010
TEST2, and later written back in TEST5.VCO_AO(3:0) and TEST5.CHP_CO(4:0) respectively. TEST5.VCO_OVERRIDE and TEST6.CHP_OVERRIDE must be set in order to make the override values to take effect.
The rest of the TESTn registers are not needed for normal operation of CC1010, but are included here for completeness.
CAL (0xE5) - PLL Calibration Control Register
Bit 7 Name
CAL_START
R/W R/W
6 5
CAL_DUAL CAL_WAIT
R/W R/W
Description 1 : Calibration started 0 : Calibration inactive Calibration is started after a positive transition on CAL_START. CAL_START must manually be written to 0 after calibration is complete (read the CAL_COMPLETE flag) 1 : Store calibration in both A and B (dual calibration) 0 : Store calibration in A or B defined by RFMAIN.F_REG 1 : Normal Calibration Wait Time (Recommended) 0 : Half Calibration Wait Time
The calibration time is proportional to the internal reference frequency fREF. See the main text. 1 : Calibration Current Doubled 0 : Normal Calibration Current (Recommended) Status bit which is set when the calibration is complete Iteration start value for calibration DAC 000 - 101: Not used 110 : Normal start value 111 : Not used
4 3 2:0
CAL_CURRENT CAL_COMPLETE CAL_ITERATE
R/W R R/W
TEST6 (0xFF) - PLL Test Register 6
Bit 7
6 5 4:0
Name
LOOPFILTER_TP1 LOOPFILTER_TP2 CHP_OVERRIDE CHP_CO(4:0)
R/W R/W
R/W R/W
Description Testpoint 1 select 0 : CHP_OUT tied to GND 1 : Select testpoint 1 to CHP_OUT Testpoint 2 select 0 : CHP_OUT tied to GND 1 : Select testpoint 2 to CHP_OUT Chargepump current override enable 0 : use calibrated value. Used in RX mode 1 : use CHP_CO[4:0] value. Used in TX mode Charge_Pump Current DAC override value, applied when CHP_OVERRIDE is high. Use 0x1B in TX mode.
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TEST5 (0xFE) - PLL Test Register 5
Bit 7:6 5
4
SmartRF a CC1010
Name
CHP_DISABLE VCO_OVERRIDE
R/W R0 R/W
R/W
3:0
VCO_AO(3:0)
R/W
Description Reserved, read as 0 PLL Charge Pump disable 0 : Charge Pump is enabled (normal function) 1 : Charge Pump is disabled VCO array override 0 : VCO array is not overridden (normal function) 1 : VCO array is set by VCO_AO(3:0) VCO Array override value
TEST4 (0xFD) - PLL Test Register 4
Bit 7:6 5:0 Name
L2KIO
R/W R/W R/W
Description Reserved, read as 0 Constant charge pump current scaling / rounding factor. Sets bandwidth of PLL. Default value is 0x25 and shall be used for all modes
TEST3 (0xFC) - PLL Test Register 3
Bit 7:5 4
3:0
Name
BREAK_LOOP CAL_DAC_OPEN (3:0)
R/W R0 R/W
R/W
Description Reserved, read as 0 Break frequency synthesis PLL 0 : PLL loop closed (normal operation) 1 : PLL loop open Calibration DAC override value, active when BREAK_LOOP is set
TEST2 (0xFB) - PLL Test Register 2
Bit 7:5 4:0 Name
CHP_CURRENT (4:0)
R/W R0 R
Description Reserved, read as 0 Status vector defining the applied charge pump current
TEST1 (0xFA) - PLL Test Register 1
Bit 7:4 3:0 Name
CAL_DAC(3:0)
R/W R0 R
Description Reserved, read as 0 Status vector defining the applied calibration DAC value
TEST0 (0xF9) - PLL Test Register 0
Bit 7:4 3:0 Name
VCO_ARRAY(3:0)
R/W R0 R
Description Reserved, read as 0 Status vector defining the applied VCO array
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Start single calibration
SmartRF a CC1010
Write FREQ_A, FREQ_B Write CAL.CAL_DUAL = 0
Frequency register A is used for RX mode, register B for TX RX frequency register A is calibrated first
Write RFMAIN: RXTX = 0; F_REG = 0; RX_PD = 0; TX_PD = 1; FS_PD = 0; CORE_PD=0; BIAS_PD=0; Write CURRENT.VCO_CURRENT = RX current Write PLL.REFDIV = RX reference divider Write TEST6=0x1B Write CAL.CAL_START=1
`RX current' is the VCO current to be used in RX mode Calibration is performed in RX mode, Result is stored in TEST0 and TEST2, RX register Calibration time depend on the reference frequency, see text.
Wait for maximum 26 ms, or Read CAL and wait until CAL.CAL_COMPLETE=1
Write CAL.CAL_START=0
Write RFMAIN: RXTX = 1; F_REG = 1 RX_PD = 1; TX_PD = 0; FS_PD = 0 CORE_PD = 0; BIAS_PD = 0; RESET_N=1
TX frequency register B is calibrated second
Write CURRENT.VCO_CURRENT = TX current Write PLL.REFDIV = TX reference divider Write TEST6 = 0x3B Write PA_POW = 0x00
`TX current' is the VCO current to be used in TX mode PA is turned off to prevent spurious emission Calibration is performed in TX mode, Result is stored in TEST0 and TEST2, TX registers
Write CAL.CAL_START=1
Wait for 26 ms, or Read CAL and wait until CAL.CAL_COMPLETE=1
Write CAL.CAL_START=0
End of calibration
Figure 30. Single calibration algorithm for RX and TX
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Start dual calibration
SmartRF a CC1010
Write FREQ_A, FREQ_B Write CAL.CAL_DUAL = 1
Frequency registers A and B are both used for RX mode (or both for TX mode)
Write RFMAIN: RXTX = 0; F_REG = 0; RX_PD = 0; TX_PD = 1; FS_PD = 0; CORE_PD=0; BIAS_PD=0; Write CURRENT.VCO_CURRENT = RX current Write PLL.REFDIV = RX reference divider Write TEST6=0x1B Write CAL.CAL_START=1
Either frequency register A or B is selected
`RX current' is the VCO current to be used in RX mode. TEST6 = 0x3B if TX mode Dual calibration is performed. Result is stored in TEST0 and TEST2, for both frequency A and B registers Calibration time depend on the reference frequency, see text.
Wait for maximum 26 ms, or Read CAL and wait until CAL.CAL_COMPLETE=1 Write CAL: CAL_START=0 End of calibration
Figure 31. Dual calibration algorithm for RX mode
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VCO, LNA and buffer current control The VCO current is programmable and should be set according to operating frequency, RX/TX mode and output power. The receiver sensitivity will also be affected by the current settings. Recommended settings for the CURRENT.VCO_CURRENT bits are shown in the CURRENT register table following below.
SmartRF a CC1010
The bias current for the LNA, and the LO and PA buffers are also programmable through FREND.LNA_CURRENT, FREND.BUF_CURRENT, CURRENT.LO_DRIVE and CURRENT.PA_DRIVE.
CURRENT (0xE1) - RF Current Control Register
Bit 7:4 Name
VCO_CURRENT (3:0)
R/W R/W
Description Control of current in VCO core for TX and RX
0000 : 150A 0001 : 250A 0010 : 350A 0011 : 450A 0100 : 950A, use for RX, f< 500 MHz 0101 : 1050A 0110 : 1150A, use for RX f>500 MHz 0111 : 1250A 1000 : 1450A, use for TX f < 500 MHz 1001 : 1550A 1010 : 1650A 1011 : 1750A 1100 : 2250A 1101 : 2350A 1110 : 2450A 1111 : 2550A, use for TX, f>500 MHz
3:2
LO_DRIVE (1:0)
R/W
00 : 0.5mA, use for TX 01 : 1.0mA, use for RX when f<500 MHz 10 : 1.5mA 11 : 2.0mA, use for RX, f>500 MHz 00 : 1mA, use for RX 01 : 2mA, use for TX, f<500 MHz 10 : 3mA 11 : 4mA, use for TX, f>500 MHz
Control of current in VCO buffer for LO drive
1:0
PA_DRIVE (1:0)
R/W
Control of current in VCO buffer for PA
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FREND (0xEE) - Front End Control Register
Bit 7:6 5
4:3
SmartRF a CC1010
Name
BUF_CURRENT LNA_CURRENT (1:0)
R/W R/W R/W
R/W
2
IF_EXTERNAL
R/W
1 0
RSSI -
R/W R/W
Description Reserved, should always be written 0 Control of current in the LNA_FOLLOWER 0 : 520uA, use for f<500 MHz 1 : 690uA, use for f>500 MHz Control of current in LNA 00 : 0.8mA 01 : 1.4mA, use for f<500 MHz 10 : 1.8mA, use for f>500 MHz 11 : 2.2mA Controls where the output from the mixer goes: 0: To internal IF filter and demodulator 1: To the AD2(RSSI/IF) pin for external filtering and demodulation 0: RSSI output disconnected from AD2(RSSI/IF)pin 1: RSSI output connected to AD2(RSSI/IF)pin Reserved, should always be written 0
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Input / Output Matching A few passive external components combined with the internal T/R switch circuitry ensures match in both RX and TX mode. The matching network is shown in Figure 32. Component values for various frequencies are given in Table 20. Component values for other frequencies (R) can be found using the SmartRF Studio software.
SmartRF a CC1010
The register MATCH should initially be set as shown in the register description below. The MATCH register is controlling a capacitor array located at the RF_OUT pin. The register can be used to fine-tune the impedance match for a particular layout and component selection. The tuning can be accomplished by stepping the register values until optimum sensitivity and output power is reached.
C41
RF_IN
TO ANTENNA C52 C51 L51 L42
RF_OUT
CC1010
AVDD=3V
Figure 32. Input/output matching network MATCH (0xDC) - Match Capacitor Array Control Register
Bit 7:3
3:0
Name
RX_MATCH (3:0) TX_MATCH (3:0)
R/W R/W
R/W
Description Selects matching capacitor array value for RX, step size is 0.4 pF 0000: Use for RF frequency > 500 MHz 1100: Use for RF frequency < 500 MHz Selects matching capacitor array value for TX, step size is 0.4 pF. Recommended setting is 0000
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Output Power Programming The RF output power is programmable and controlled by the PA_POW register. Table 29 shows the closest programmable value for output powers in steps of 1 dB. The typical current consumption is also
SmartRF a CC1010
shown for a 14.7456 MHz main oscillator frequency. In power down mode the PA_POW should be set to 0x00 for minimum leakage current.
Table 29. Output power settings and typical current consumption
Output power
[dBm] RF frequency 433 MHz PA_POW Current consumption, typ. [mA] RF frequency 868 MHz PA_POW Current consumption, typ. [mA]
-20 0x02 21.7 0x02 24.2 -19 0x02 21.7 0x02 24.2 -18 0x02 21.7 0x03 24.4 -17 0x02 21.7 0x03 24.4 -16 0x02 21.7 0x04 24.6 -15 0x02 21.7 0x04 24.6 -14 0x03 21.9 0x05 24.8 -13 0x03 21.9 0x06 25 -12 0x04 22.2 0x07 25.2 -11 0x04 22.2 0x08 25.4 -10 0x05 22.4 0x09 25.7 -9 0x05 22.4 0x0A 25.9 -8 0x06 22.7 0x0B 26 -7 0x07 22.9 0x0C 26.2 -6 0x08 23.2 0x0E 26.6 -5 0x09 23.5 0x0F 26.8 -4 0x0A 23.8 0x50 29.3 -3 0x0B 24.0 0x60 29.9 -2 0x0D 24.5 0x70 30.5 -1 0x0E 24.9 0x80 31.0 0 0x40 26.0 0xA0 32.1 1 0x50 27.0 0xC0 33.1 2 0x60 28.0 0xE0 34.2 3 0x60 28.0 0xF0 34.7 4 0x70 28.9 0xFF 38.5 5 0x80 30.0 6 0x90 31.0 7 0xB0 33.2 8 0xC0 34.3 9 0xE0 36.7 10 0xFF 42.8 Note: The current consumption is measured at for a 14.7456 MHz main oscillator frequency and appy for crystal frequencies in the range 8 - 16 MHz. For a crystal frequency in the range 3-8 MHz, subtract approximately 5 mA. For a crystal frequency in the range 3-8 MHz, add approximately 5 mA.
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SmartRF a CC1010
PA_POW (0xE2) - PA Output Power Control Register
Bit 7:4
3:0
Name
PA_HIGHPOWER (3:0) PA_LOWPOWER (3:0)
R/W R/W
R/W
Description Control of output power in high power array. Should be 0000 in PD mode. See Table 29 for details. Control of output power in low power array. Should be 0000 in PD mode. See Table 29 for details.
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RSSI Output
SmartRF a CC1010
CC1010 has a built-in RSSI (Received Signal Strength Indicator) giving an analog output signal at the AD2(RSSI/IF) pin. RSSI is enabled when setting FREND.RSSI (see page 111). The output current of this pin is then inversely proportional to the input signal level. The output should be terminated in a resistor to convert the current output into a voltage. A capacitor is used to low-pass filter the signal.
The RSSI voltage range is from 0 - 1.2 V when using a 27 k terminating resistor, giving approximately 50 dB/V. This RSSI voltage can be measured by the on-chip A/D converter using the AD2 input. Note that a higher voltage means a lower input signal.
The RSSI measures the power referred to the RF_IN pin. The input power can be calculated using the following equations: P = -48.8 VRSSI- 57.2 [dBm] at 433 MHz P = -46.9 VRSSI- 53.9 [dBm] at 868 MHz The external network for RSSI operation is shown in Figure 33. R281 = 27 k, C281 = 1nF. A typical plot of RSSI voltage as function of input power is shown in Figure 34. When using the on-chip A/D converter, set ADCON = 0x06 to initiate a single conversion using VDD as reference. The converted RSSI voltage can then be read from the ADDATH and ADDATL registers.
CC1010
AD2 (RSSI/IF)
Voltage
C281
R281
1,3 1,2 1,1 1 0,9 0,8 0,7 0,6 0,5 0,4 0,3 0,2 0,1 0
-105 -100 -95 -90 -85 -80 -75 -70 -65
433Mhz 868Mhz
-60
-55
-50
dBm
Figure 33. RSSI circuit
Figure 34. Typical RSSI voltage vs. input power
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IF output
SmartRF a CC1010
CC1010 has a built-in 10.7 MHz IF output buffer. This buffer can be used in applications requiring image frequency rejection. The system is then built with CC1010, a 10.7 MHz ceramic filter and an external 10.7 MHz demodulator. The network matching an external IF filter is
AD2 (RSSI/IF)
shown in Figure 35. R281 = 470 , C281 = 3.3nF. This external network provides 330 source impedance for the 10.7 MHz ceramic filter.
CC1010
C281 R281
To 10.7MHz filter and demodulator
Figure 35. IF Output
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Optional LC Filter An optional low-pass LC filter may be added between the antenna and the matching network in certain applications. The filter will reduce the emission of harmonics and increase the receiver selectivity. The filter topology is shown in Figure 36. Component values are given in Table 30. The filter is designed for 50 terminations. The component values may have to be tuned to compensate for layout parasitics.
SmartRF a CC1010
The design equations for a 3dB equal ripple filter are:
1 ae o C 2 f RF c / e 1 - 0.1333 o L= 35.6 0.067 ,C= C C
where c is the cut-off frequency and fRF is the transmitted RF frequency.
L71 C71 C72
Figure 36. LC Filter
Table 30. LC Filter component values
Item
C71 C72 L71
315 MHz
30 pF 30 pF 15 nH
434 MHz
20 pF 20 pF 12 nH
869 MHz
10 pF 10 pF 5.6 nH
915 MHz
10 pF 10 pF 4.7 nH
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Reserved registers and test registers The CC1010 contains a few registers intended for test purposes only. Normally these registers should not be written. The FSHAPEn, FSDELAY and FSCTRL registers are reserved for future use. A separate reset signal for the PLL is available in FSCTRL.FS_RESET_N. This will reset the frequency divider part of the PLL. The reset is active when a zero is written, and a one must be written for the reset to be released. FSCTRL.EXT_FILTER can be set in order
SmartRF a CC1010
to use an external PLL loop filter. However, this is not recommended in a normal application. The PRESCALER register controls the prescaler current, and should always be set to 0x00 (which is the reset state). The TESTMUX register is not needed for normal operation of CC1010, but are included here for completeness. TESTMUX should always be set to 0x00.
Table 31. TESTMUX modes
TESTMUX 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
P0.2
Normal operation CLK_REF LOCK_DET_CONTINUOUS SER_PAR_IRQ RTC_IRQ ANALOG_ALARM_H MODEM_BIT_CLK MODEM_BIT_CLK ADC_SAR_ADCCLK_EN CLK_RTC DES_DEBUG_0 DES_DEBUG_1 DES_DEBUG_2 DES_DEBUG_3 FLASH_WRITE_IRQ CAL_DIG_COMPLETE
P0.1
Normal operation CLK_PHASE_DET_OUT LOCK_DET_INSTANT TIMER2_IRQ ADC_IRQ ANALOG_ALARM_L MODEM_RX_DATA MODEM_TX_DATA ANALOG_COMP RTC_IRQ
P0.0
Normal operation MODEM_TX_OUT ANALOG_WINDOW_SYNC TIMER3_IRQ DES_IRQ CAL_DIG_COMPLETE ANALOG_IF_OUT MODEM_TX_OUT ADC_SAR_EOC CLK_UC
FSHAPEn (0xF1 - 0xF7), n1..7 - Frequency Shaping Register n
Bit 7:5 4:0 Name
FSHAPEn (4:0)
R/W R0 R/W
Description Reserved, read as 0 Reserved for future use.
FSDELAY (0xE9) - Frequency Shaping Delay Control Register
Bit 7:0 Name
FSDELAY (7:0)
R/W R/W
Description Reserved for future use.
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SmartRF a CC1010
FSCTRL (0xEC) - Frequency Synthesiser Control Register
Bit 7:5 4
3 2 1 0
Name
EXT_FILTER DITHER1 DITHER0 SHAPE FS_RESET_N
R/W R0 R/W
R/W R/W R/W R/W
Description Reserved, read as 0 Setting for external loop filter (not recommended) 0 : Internal loop filter (recommended) 1 : External loop filter Reserved for future use. Write as 0.
Reserved for future use. Write as 0. Reserved for future use. Write as 0. Separate reset of frequency synthesiser 0 : Frequency synthesiser is reset 1 : Frequency synthesiser reset is released
PRESCALER (0xE6) - Prescaler Control Register
Bit 7 Name
PRE_SWING (1:0)
R/W R/W
5
PRE_CURRENT (1:0)
R/W
3 2
IF_INPUT IF_FRONT
R/W R/W
1 0
-
R/W R/W
Description Prescaler swing. Fractions for PRE_CURRENT[1:0] = 00 00 : 1 * Nominal Swing 01 : 2/3 * Nominal Swing 10 : 7/3 * Nominal Swing 11 : 5/3 * Nominal Swing Prescaler current scaling 00 : 1 * Nominal Current 01 : 2/3 * Nominal Current 10 : 1/2 * Nominal Current 11 : 2/5 * Nominal Current 0 : Nominal setting 1 : AD2(RSSI/IF) pin is input to IF-strips 0 : Nominal setting 1 : Output of IF_Front_amp is switched to the AD2(RSSI/IF) pin Reserved for future use, always write 0
Reserved for future use, always write 0
TESTMUX (0xEF) - Test Multiplexer Control Register (for prototype testing)
Bit 7:4 3:0 Name
TESTMUX (3:0)
R/W R0 R/W
Description Reserved, read as 0 Select internal test signals to be output to P0(2:0). This function is enabled when TESTMUX 0000. The port directions are still set by P0DIR.
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System Considerations and Guidelines SRD regulations International regulations and national laws regulate the use of radio receivers and transmitters. SRDs (Short Range Devices) for licence free operation are allowed to operate in the 433 and 868-870 MHz bands in most European countries. In the United States such devices operate in the 260-470 and 902-928 MHz bands. CC1010 is designed to meet the requirements for operation in all these bands. A summary of the most important aspects of these regulations can be found in Application Note AN001 SRD regulations for licence free transceiver operation, available from Chipcon's web site. Low cost systems In systems where low cost is of great importance the CC1010 is the ideal choice. Very few external components keep the total cost at a minimum. The oscillator crystal can then be a low cost crystal with 50/25 ppm frequency tolerance at 433/868 MHz respectively. Battery operated systems In low power applications the RF Transceiver power down mode should be used when no communication takes place. Using receiver polling, that is, listening for transmissions for a few milliseconds at regular intervals, will also save a lot of battery power. The RSSI can be used as a first indication that a transmission is received. See page 84 for information on how effective power management can be implemented. Utilizing the Idle mode and Power down modes and clock modes of the MCU will also reduce the power consumption significantly. See page 31 for details. Narrow-band systems CC400 and CC900 are recommended for best performance in narrow-band applications. The phase noise of CC400 and CC900 is superior and for systems
SmartRF a CC1010
with 25 kHz channel spacing or less. With strict requirements to ACP (Adjacent Channel Power), low phase noise is important. The selectivity of CC1010 can be improved by using an external ceramic filter and demodulator at 10.7 MHz. Such ceramic filters are typically 180 or 280 kHz wide. A unique feature in CC1010 is the very fine frequency resolution of < 250 Hz. This can be used to do the temperature compensation of the crystal if the temperature drift curve is known and a temperature sensor is included in the system. Even initial adjustment can be done using the frequency programmability. This eliminates the need for an expensive TCXO and trimming in some applications. In less demanding applications a crystal with low temperature drift and low ageing could be used without further compensation. A trimmer capacitor in the crystal oscillator circuit (in parallel with C171) could be used to set the initial frequency accurately. The fine frequency step programming cannot be used in RX mode if optimised frequency settings are required (see page 103). High reliability systems Using a SAW filter as a preselector between the antenna and the RF input will improve the communication reliability in harsh environments by reducing the probability of blocking. The receiver sensitivity and the output power will be reduced due to the filter insertion loss. By inserting the filter in the RX path only, together with an external RX/TX switch, only the receiver sensitivity is reduced, and output power is unaffected. Any general-purpose I/O pins can be configured to control an external LNA, RX/TX switch or power amplifier. Frequency hopping spread spectrum systems Due to the very fast frequency shift properties of the PLL, the CC1010 is very
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suitable for frequency hopping systems. Hop rates of 10-1000 hops/s are usually used depending on the bit rate and the amount of data to be sent during each transmission. The two frequency registers (FREQ_A and FREQ_B) are designed such that the `next' frequency can be programmed while the `present' frequency is used. The switching between the two frequencies is done through the RFMAIN.F_REG control bit. Frequency hopping improve the reliability and increase the security in a wireless link. The US ISM band at 902 - 928 MHz is very suitable for frequency hopping protocols.
SmartRF a CC1010
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SmartRF a CC1010
PCB Layout Recommendations Chipcon provide reference layouts that should be followed in order to achieve the best performance. The reference designs can be downloaded from the Chipcon website. A four layer PCB is highly recommended. The top layer should be used for signal routing, and the open areas should be filled with metallisation connected to ground using several vias. The second layer of the PCB should be the "groundplane". Layer three is used for power supply and layer four for general routing and decoupling. A few components are also placed at the reverse side (VCO inductor and power filtering). The ground pins should be connected to ground as close as possible to the package pin using individual vias for each Antenna Considerations pin. The de-coupling capacitors should also be placed as close as possible to the supply pins and connected to the ground plane by separate vias. The external components should be as small as possible and surface mount devices are required. The VCO inductor must be placed as close as possible to the chip and symmetrical with respect to the input pins. It is important to keep the coupling between the VCO inductor and the matching network very low in order to reduce LO leakage. Due to this the VCO inductor is placed at the reverse side of the PCB. A development kit with a fully assembled PCB is available, and can be used as a guideline for layout.
CC1010 can be used together with various types of antennas. The most common antennas for short-range devices are monopole, helical and loop antennas.
Monopole antennas are resonant antennas with a length corresponding to one quarter of the electrical wavelength (/4). They are very easy to design and can be implemented simply as a "piece of wire" or even integrated into the PCB. Non-resonant monopole antennas shorter than /4 can also be used, but at the expense of range. In size and cost critical applications such an antenna may very well be integrated into the PCB. Helical antennas can be thought of as a combination of a monopole and a loop antenna. They are a good compromise in size critical applications. But helical antennas tend to be more difficult to optimise than the simple monopole. Loop antennas are easy to integrate into the PCB, but are less effective due to
difficult impedance matching because of their very low radiation resistance if they are made small. For low power applications the /4monopole antenna is recommended giving the best range and because of its simplicity. The length of the /4-monopole antenna is given by: L = 7125 / f where f is in MHz, giving the length in cm. An antenna for 869 MHz should be 8.2 cm, and 16.4 cm for 434 MHz. The antenna should be connected as close as possible to the IC. If the antenna is located away from the input pin the antenna should be matched to the feeding transmission line (50 ). For a more thorough primer on antennas, please refer to Application Note AN003 SRD Antennas available from Chipcon's web site.
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Package Description (TQFP-64)
SmartRF a CC1010
CC1010 is packaged in a TQFP-64 package. The package is shown in Figure 37 below and the dimensions are listed in Table 32. Please note that the drawing in Figure 37 is not to scale.
Figure 37. TQFP-64 package
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 123 of 133
Chipcon
SmartRF a CC1010
Table 32. TQFP-64 package dimensions
Symbol A A1 A2 D D1 D3 E E1 E3 R1 R2 1 2 3 C L L1 S Ccc Ddd e b Dimensions (mm) 1.20 max 0.05 - 0.15 1.00 0.05 12.00 0.20 9.95 0.10 10.00 0.10 12.00 0.20 9.95 0.10 10.00 0.10 0.08 Min 0.15 Ref. 0 - 7 0 Min 12 12 0.09 - 0.20 0.60 0.15 1.0 Ref 0.20 Min. 0.080 Max 0.080 Max 0.50 0.17 - 0.27 Remarks Overall height Standoff Package thickness Terminal dimension Top package width Bottom package width Terminal dimension Top package length Bottom package length First radius Second radius Foot angle Shoulder angle Top draft angle Bottom draft angle Lead thickness Foot length Lead length Coplanarity Bent lead Lead pitch Lead tip width
Soldering Information
Recommended soldering profile is according to CECC 00 802, Edition 3.
Tray Specification
TQFP-64 antistatic tray, 8 by 20 devices.
Tray Specification Tray Width Tray Length Tray Height 135.9 mm 322.6 mm 7.62 mm
Package TQFP-64
Units per Tray 160
Carrier Tape and Reel Specification
Carrier tape and reel is in accordance with EIA Specification 481.
Tape and Reel Specification Component Hole Reel Pitch Pitch Diameter 16 mm 4 mm 13"
Package TQFP-64
Tape Width 24 mm
Units per Reel 1500
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 124 of 133
Chipcon
List of Abbreviations
* * * * * * * * * * * * * * * * * * * * ADC - Analog to Digital Converter AMR - Automatic Meter Reading CFB - Cipher Feedback Mode CMOS - Complementary Metal Oxide Semiconductor CPU - Central Processor Unit DES - Data Encryption Standard DMA - Direct Memory Access FCC - Federal Communication Committee FSK - Frequency Shift Keying IDE - Integrated Development Environment IF - Intermediate Frequency ISM - Industrial Scientific Medical ISR - Interrupt Service Routine LNA - Low Noise Amplifier LO - Local Oscillator LPF - Loop Filter LSB - Least Significant Bit (or Byte) MOQ - Minimum Order Quantity MSB - Most Significant Bit (or Byte) NRZ - Non Return to Zero
SmartRF a CC1010
* * * * * * * * * * * * * * * * * * * * *
OFB - Output Feedback Mode PCB - Printed Circuit Board PLL - Phase Locked Loop POR - Power On Reset PWM - Pulse Width Modulation RAM - Random Access Memory RF - Radio Frequency RSSI - Received Signal Strength Indicator RTC - Real-Time Clock RX - Receive SFR - Special Function Register SPI - Serial Peripheral Interface SRAM - Static RAM SRD - Short Range Device TQFP - Thin Quad Flat Pack TBD - To Be Defined TX - Transmit UART - Universal Asynchronous Receiver/Transmitter UHF - Ultra High Frequency VCO - Voltage Controlled Oscillator XOSC - Crystal Oscillator
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 125 of 133
Chipcon
SmartRF a CC1010
SFR Summary
A summary of all SFRs with address, register names, bit names and reset values are shown in Table 33 below.
Table 33. SFR Summary (sorted by address)
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Page
Addr
Name
Bit 7
Bit 6
0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B
P0 SP DPL0 DPH0 DPL1 DPH1 DPS PCON TCON TMOD TL0 TL1 TH0 TH1 CKCON P1 EXIF MPAGE ADCON ADDATL ADDATH ADCON2 ADTRH SCON0 SBUF0 . -
P0.7 SP.7 DPL0.7 DPH0.7 DPL1.7 DPH1.7 SMOD0 TF1 GATE TL0.7 TL1.7 TH0.7 TH1.7 P1.7 TF3 MPAGE7 AD_PD ADDAT7 ADCIE ADTRH7 SM0_0 SBUF0.7 -
P0.6 SP.6 DPL0.6 DPH0.6 DPL1.6 DPH1.6 TR1 C/T TL0.6 TL1.6 TH0.6 TH1.6 P1.6 ADIF MPAGE6 ADDAT6 ADCIF ADTRH6 SM1_0 SBUF0.6 -
P0.5 SP.5 DPL0.5 DPH0.5 DPL1.5 DPH1.5 TF0 M1 TL0.5 TL1.5 TH0.5 TH1.5 T2M P1.5 TF2 MPAGE5 ADCM1 ADDAT5 ADCDIV5 ADTRH5 SM2_0 SBUF0.5 . -
P0.4 SP.4 DPL0.4 DPH0.4 DPL1.4 DPH1.4 TR0 M0 TL0.4 TL1.4 TH0.4 TH1.4 T1M P1.4 RFIF MPAGE4 ADCM0 ADDAT4 ADCDIV4 ADTRH4 REN_0 SBUF0.4 . -
P0.3 SP.3 DPL0.3 DPH0.3 DPL1.3 DPH1.3 GF1 IE1 GATE TL0.3 TL1.3 TH0.3 TH1.3 T0M P1.3 MPAGE3 ADCREF ADDAT3 ADCDIV3 ADTRH3 TB8_0 SBUF0.3 . -
P0.2 SP.2 DPL0.2 DPH0.2 DPL1.2 DPH1.2 GF0 IT1 C/T TL0.2 TL1.2 TH0.2 TH1.2 MD2 P1.2 MPAGE2 ADCRUN ADDAT2 ADCDIV2 ADTRH2 RB8_0 SBUF0.2 . -
P0.1 SP.1 DPL0.1 DPH0.1 DPL1.1 DPH1.1 STOP IE0 M1 TL0.1 TL1.1 TH0.1 TH1.1 MD1 P1.1 MPAGE1 ADADR1 ADDAT1 ADDAT9 ADCDIV1 ADTRH1 TI_0 SBUF0.1 . -
P0.0 SP.0 DPL0.0 DPH0.0 DPL1.0 DPH1.0 SEL IDLE IT0 M0 TL0.0 TL1.0 TH0.0 TH1.0 MD0 P1.0 MPAGE0 ADADR0 ADDAT0 ADDAT8 ADCDIV0 ADTRH0 RI_0 SBUF0.0 . -
00001111 00000111 00000000 00000000 00000000 00000000 00000000 00110000 00000000 00000000 00000000 00000000 00000000 00000000 00000001 00000000 11111111 00001000 00000000 10000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
45 21 19 19 19 19 20 32 50 49 48 48 48 48 51 45 28 20 76 76 76 77 77 63 63 -
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 126 of 133
Chipcon
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
SmartRF a CC1010
Page
Addr
Name
Bit 7
Bit 6
0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF
CHVER P2 SPCR SPDR SPSR P0DIR P1DIR P2DIR P3DIR IE TCON2 T2PRE T3PRE T2 T3 FLADR FLCON P3 CRPINI0 CRPINI1 CRPINI2 CRPINI3 IP RDATA RADRL RADRH CRPINI4 CRPINI5 CRPINI6 CRPINI7
CHIP_TYPE5 P2.7 SPDR7 P1DIR7 P2DIR7 EA T2PRE7 T3PRE7 T2.7 T3.7 FLADR7 P3.7 CRPINI0.7 CRPINI1.7 CRPINI2.7 CRPINI3.7 RDATA7 RADR15 RADR7 CRPINI4.7 CRPINI5.7 CRPINI6.7 CRPINI7.7
CHIP_TYPE4 P2.6 SPDR6 P1DIR6 P2DIR6 T2PRE6 T3PRE6 T2.6 T3.6 FLADR6 FLASH_LP1 P3.6 CRPINI0.6 CRPINI1.6 CRPINI2.6 CRPINI3.6 RDATA6 RADR14 RADR6 CRPINI4.6 CRPINI5.6 CRPINI6.6 CRPINI7.6
CHIP_TYPE3 P2.5 SPE SPDR5 P1DIR5 P2DIR5 P3DIR5 T2PRE5 T3PRE5 T2.5 T3.5 FLADR5 FLASH_LP0 P3.5 CRPINI0.5 CRPINI1.5 CRPINI2.5 CRPINI3.5 RDATA5 RADR13 RADR5 CRPINI4.5 CRPINI5.5 CRPINI6.5 CRPINI7.5
CHIP_TYPE2 P2.4 DORD SPDR4 P1DIR4 P2DIR4 P3DIR4 ES0 T2PRE4 T3PRE4 T2.4 T3.4 FLADR4 WRFLASH P3.4 CRPINI0.4 CRPINI1.4 CRPINI2.4 CRPINI3.4 PS0 RDATA4 RADR12 RADR4 CRPINI4.4 CRPINI5.4 CRPINI6.4 CRPINI7.4
CHIP_TYPE1 P2.3 CPOL SPDR3 P0DIR3 P1DIR3 P2DIR3 P3DIR3 ET1 TR3 T2PRE3 T3PRE3 T2.3 T3.3 FLADR3 RMADR3 P3.3 CRPINI0.3 CRPINI1.3 CRPINI2.3 CRPINI3.3 PT1 RDATA3 RADR11 RADR3 CRPINI4.3 CRPINI5.3 CRPINI6.3 CRPINI7.3
CHIP_TYPE0 P2.2 CPHA SPDR2 P0DIR2 P1DIR2 P2DIR2 P3DIR2 EX1 M3 T2PRE2 T3PRE2 T2.2 T3.2 FLADR2 RMADR2 P3.2 CRPINI0.2 CRPINI1.2 CRPINI2.2 CRPINI3.2 PX1 RDATA2 RADR10 RADR2 CRPINI4.2 CRPINI5.2 CRPINI6.2 CRPINI7.2
CHIP_REV1 P2.1 SPR1 SPDR1 SPA P0DIR1 P1DIR1 P2DIR1 P3DIR1 ET0 TR2 T2PRE1 T3PRE1 T2.1 T3.1 FLADR1 RMADR1 P3.1 CRPINI0.1 CRPINI1.1 CRPINI2.1 CRPINI3.1 PT0 RDATA1 RADR9 RADR1 CRPINI4.1 CRPINI5.1 CRPINI6.1 CRPINI7.1
CHIP_REV0 P2.0 SPR0 SPDR0 WCOL P0DIR0 P1DIR0 P2DIR0 P3DIR0 EX0 M2 T2PRE0 T3PRE0 T2.0 T3.0 FLADR0 RMADR0 P3.0 CRPINI0.0 CRPINI1.0 CRPINI2.0 CRPINI3.0 PX0 RDATA0 RADR8 RADR0 CRPINI4.0 CRPINI5.0 CRPINI6.0 CRPINI7.0
00000000 00000000 00000000 00000000 11111111 00000000 00000000 00000000 00001111 11111111 11111111 00111111 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 11111111 00000000 00000000 00000000 00000000 00000000 00000000 00000000 10000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
42 46 67 67 68 46 46 47 47 27 54 55 55 55 55 39 40 46 73 73 73 73 29 42 42 42 73 73 73 73
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 127 of 133
Chipcon
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
SmartRF a CC1010
Page
Addr
Name
Bit 7
Bit 6
0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA BAUDRATE0 RX_MATCH1 FLWCTIME5 ACC5 VCO_CURRENT1 DATA_FORMAT1 RX_MATCH0 FLWCTIME4 ACC4 VCO_CURRENT0 DATA_FORMAT0 TX_MATCH3 FLWCTIME3 ACC3 LO_DRIVE1 XOSC_FREQ2 TX_MATCH2 FLWCTIME2 ACC2 LO_DRIVE0 XOSC_FREQ1 TX_MATCH1 FLWCTIME1 ACC1 PA_DRIVE1
SCON1 SBUF1 RFCON CRPCON CRPKEY CRPDAT CRPCNT RANCON RFMAIN RFBUF FREQ_0A FREQ_1A FREQ_2A FREQ_0B FREQ_1B FREQ_2B PSW X32CON WDT PDET BSYNC EICON MODEM2 MODEM1
SM0_1 SBUF1.7 CRPKEY7 CRPDAT7 CRPCNT7 RXTX RFBUF7 FREQ_A7 FREQ_A15 FREQ_A23 FREQ_B7 FREQ_B15 FREQ_B23 CY PEN BSYNC7 -
SM1_1 SBUF1.6 CRPIE CRPKEY6 CRPDAT6 CRPCNT6 F_REG RFBUF6 FREQ_A6 FREQ_A14 FREQ_A22 FREQ_B6 FREQ_B14 FREQ_B22 AC PLEN6 BSYNC6 PLO6 LOCK_AVG_IN
SM2_1 SBUF1.5 CRPIF CRPKEY5 CRPDAT5 CRPCNT5 RX_PD RFBUF5 FREQ_A5 FREQ_A13 FREQ_A21 FREQ_B5 FREQ_B13 FREQ_B21 F0 PLEN5 BSYNC5 FDIE PLO5 LOCK_AVG_MO
REN_1 SBUF1.4 MVIOL LOADKEYS CRPKEY4 CRPDAT4 CRPCNT4 TX_PD RFBUF4 FREQ_A4 FREQ_A12 FREQ_A20 FREQ_B4 FREQ_B12 FREQ_B20 RS1 WDTSE PLEN4 BSYNC4 FDIF PLO4 LOCK_AVG_STA
TB8_1 SBUF1.3 MLIMIT2 CRPMD CRPKEY3 CRPDAT3 CRPCNT3 FS_PD RFBUF3 FREQ_A3 FREQ_A11 FREQ_A19 FREQ_B3 FREQ_B11 FREQ_B19 RS0 WDTEN PLEN3 BSYNC3 RTCIF PLO3 SETTLING1
RB8_1 SBUF1.2 MLIMIT1 ENCDEC CRPKEY2 CRPDAT2 CRPCNT2 CORE_PD RFBUF2 FREQ_A2 FREQ_A10 FREQ_A18 FREQ_B2 FREQ_B10 FREQ_B18 OV X32_BYPASS WDTCLR PLEN2 BSYNC2 PLO2 SETTLING0
TI_1 SBUF1.1 MLIMIT0 TRIDES CRPKEY1 CRPDAT1 CRPCNT1 RANEN BIAS_PD RFBUF1 FREQ_A1 FREQ_A9 FREQ_A17 FREQ_B1 FREQ_B9 FREQ_B17 F1 X32_PD WDTPRE1 PLEN1 BSYNC1 PLO1 PEAKDETECT
RI_1 SBUF1.0 BYTEMODE CRPEN CRPKEY0 CRPDAT0 CRPCNT0 RANBIT RFBUF0 FREQ_A0 FREQ_A8 FREQ_A16 FREQ_B0 FREQ_B8 FREQ_B16 P CMODE WDTPRE0 PLEN0 BSYNC0 PLO0 MODEM_RESET XOSC_FREQ0 TX_MATCH0 FLWCTIME0 ACC0 PA_DRIVE0
00000000 00000000 00000110 00000000 00000000 00000000 00000000 00000000 00111000 00000000 11001011 10100000 01110101 01001110 10100101 01110101 00000000 00000010 00001011 00000000 00000000 00000000 00000000 00000000 01000000 00010110 00101111 01110001 00000000 00001010 00000000 00000000 00000000 11001010
64 63 95 72 72 72 72 74 84 90 101 100 100 101 101 101 21 33 58 96 96 28 95 93 88 112 40 21 110
0xDB 0xDC 0xDD 0xDE 0xDF 0xE0 0xE1
MODEM0 MATCH FLTIM ACC CURRENT
BAUDRATE2 RX_MATCH3 ACC7 VCO_CURRENT3
BAUDRATE1 RX_MATCH2 ACC6 VCO_CURRENT2
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 128 of 133
Chipcon
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
SmartRF a CC1010
Page
Addr
Name
Bit 7
Bit 6
0xE2 REFDIV2 CAL_WAIT PRE_CURRENT1 RESERVED.5 FSDELAY5 FSEP5 RT5 LNA_BUF_CUR B.5 FSHAPE7.5 FSHAPE6.5 FSHAPE5.5 FSHAPE4.5 FSHAPE3.5 FSHAPE2.5 FSHAPE1.5 L2KIO0.5 CHP_DISABLE CHP_OVERRIDE L2KIO0.4 VCO_OVERRIDE CHP_CO4 RESERVED.4 RTCIE FSDELAY4 FSEP4 EXT_FILTER RT4 LNA_CURRENT1 B.4 FSHAPE7.4 FSHAPE6.4 FSHAPE5.4 FSHAPE4.4 FSHAPE3.4 FSHAPE2.4 FSHAPE1.4 PRTC CHP_CURRENT4 BREAK_LOOP CAL_CURRENT PRE_CURRENT0 CAL_ITERATE1 PRESCALE.1 LOCK_INSTANT REFDIV1 REFDIV0 ALARM_DISABL ALARM_H
PA_POW
PA_HIGHPOWER
PA_HIGHPOWER
PA_HIGHPOWER
PA_HIGHPOWER
PA_LOWPOWER
PA_LOWPOWER
PA_LOWPOWER
PA_LOWPOWER ALARM_L
00001111 000100xx 000000xx 00000101 00000000 00000000 11100000 00101111 01011001 00000000 00000001 00000000 00000000 00000000 00000000 00011100 00010110 00010000 00001010 00000110 00000011 00000001 11100000 0000xxxx 0000xxxx 000xxxxx 00000100 00100101 00001000 00010000
113 101 102 106 118 42 27 118 101 101 119 61 111 119 21 118 118 118 118 118 118 118 29 107 107 107 107 107 107 106
0xE3
PLL
REFDIV4
REFDIV3
0xE4
LOCK
-
-
0xE5 0xE6
CAL PRESCALE
CAL_START PRE_SWING1
CAL_DUAL PRE_SWING0
PLL_LOCK_ ACCURACY CAL_COMPLETE IF_INPUT
PLL_LOCK_ LENGTH CAL_ITERATE2 IF_FRONT
LOCK_ CONTINUOUS CAL_ITERATE0 PRESCALE.0
0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC
RESERVED EIE FSDELAY FSEP0 FSEP1 FSCTRL RTCON FREND TESTMUX B FSHAPE7 FSHAPE6 FSHAPE5 FSHAPE4 FSHAPE3 FSHAPE2 FSHAPE1 EIP TEST0 TEST1 TEST2 TEST3
RESERVED.7 FSDELAY7 FSEP7 RTEN B.7 FSHAPE7.7 FSHAPE6.7 FSHAPE5.7 FSHAPE4.7 FSHAPE3.7 FSHAPE2.7 FSHAPE1.7 -
RESERVED.6 FSDELAY6 FSEP6 RT6 B.6 FSHAPE7.6 FSHAPE6.6 FSHAPE5.6 FSHAPE4.6 FSHAPE3.6 FSHAPE2.6 FSHAPE1.6 -
0xFD 0xFE 0xFF
TEST4 TEST5 TEST6
LOOPFILTER_ TP1
LOOPFILTER_ TP2
RESERVED.3 ET3 FSDELAY3 FSEP3 DITHER1 RT3 LNA_CURRENT0 TESTSEL3 B.3 FSHAPE7.3 FSHAPE6.3 FSHAPE5.3 FSHAPE4.3 FSHAPE3.3 FSHAPE2.3 FSHAPE1.3 PT3 VCO_ARRAY3 CAL_DAC3 CHP_CURRENT3 CAL_DAC_ OPEN3 L2KIO0.3 VCO_AO3 CHP_CO3
RESERVED.2 ADIE FSDELAY2 FSEP2 FSEP10 DITHER0 RT2 IF_EXTERNAL TESTSEL2 B.2 FSHAPE7.2 FSHAPE6.2 FSHAPE5.2 FSHAPE4.2 FSHAPE3.2 FSHAPE2.2 FSHAPE1.2 PAD VCO_ARRAY2 CAL_DAC2 CHP_CURRENT2 CAL_DAC_ OPEN2 L2KIO0.2 VCO_AO2 CHP_CO2
RESERVED.1 ET2 FSDELAY1 FSEP1 FSEP9 SHAPE RT1 RSSI TESTSEL1 B.1 FSHAPE7.1 FSHAPE6.1 FSHAPE5.1 FSHAPE4.1 FSHAPE3.1 FSHAPE2.1 FSHAPE1.1 PT2 VCO_ARRAY1 CAL_DAC1 CHP_CURRENT1 CAL_DAC_ OPEN1 L2KIO0.1 VCO_AO1 CHP_CO1
RESERVED.0 RFIE FSDELAY0 FSEP0 FSEP8 FS_RESET_N RT0 TESTSEL0 B.0 FSHAPE7.0 FSHAPE6.0 FSHAPE5.0 FSHAPE4.0 FSHAPE3.0 FSHAPE2.0 FSHAPE1.0 PRF VCO_ARRAY0 CAL_DAC0 CHP_CURRENT0 CAL_DAC_ OPEN0 L2KIO0.0 VCO_AO0 CHP_CO0
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 129 of 133
Chipcon
Alphabetic Register Index
SmartRF a CC1010
ACC (0xE0) - Accumulator Register ........................................................................................ 21 ADCON (0x93) - ADC Control Register ................................................................................... 76 ADCON 2(0x96) - ADC Control Register 2.............................................................................. 77 ADDATH (0x95) - ADC Data Register, High Bits..................................................................... 76 ADDATL (0x94) - ADC Data Register, Low Byte..................................................................... 76 ADTRH (0x97) - ADC Threshold Register ............................................................................... 77 B (0xF0) - B Register ............................................................................................................... 21 BSYNC (0xD4) - Byte Synchronisation Register ..................................................................... 96 CAL (0xE5) - PLL Calibration Control Register ..................................................................... 106 CHVER (0x9F) - Chip Version / Revision Register.................................................................. 42 CKCON (0x8E) - Timer Clock rate Control Register................................................................ 51 CRPCNT (0xC6) - Encryption / Decryption Counter ............................................................... 72 CRPCON (0xC3) - Encryption / Decryption Control Register .................................................. 72 CRPDAT (0xC5) - Encryption / Decryption Data Location Register ........................................ 72 CRPINIn, n{0..7} (0xB4-0xB7, 0xBC-0xBF) - DES Initialisation Vector ................................ 73 CRPKEY (0xC4) - Encryption / Decryption Key Location Register ......................................... 72 CURRENT (0xE1) - RF Current Control Register.................................................................. 110 DPH0 (0x83) - Data Pointer 0, high byte ................................................................................. 19 DPH1 (0x85) - Data Pointer 1, high byte ................................................................................. 19 DPL0 (0x82) - Data Pointer 0, low byte ................................................................................... 19 DPL1 (0x84) - Data Pointer 1, low byte ................................................................................... 19 DPS (0x86) - Data Pointer Select ............................................................................................ 20 EICON (0xD8) - Extended Interrupt Control ............................................................................ 28 EIE (0xE8) - Extended Interrupt Enable Register .................................................................... 27 EIP (0xF8) - Extended Interrupt Priority Register .................................................................... 29 EXIF (0x91) - Extended Interrupt Flag..................................................................................... 28 FLADR (0xAE) - Flash Write Address Register ....................................................................... 39 FLCON (0xAF) - Flash Write Control Register ........................................................................ 40 FLTIM (0xDD) - Flash Write Timing Register .......................................................................... 40 FREND (0xEE) - Front End Control Register ........................................................................ 111 FREQ_0A (0xCA) - Frequency A, Control Register 0........................................................... 101 FREQ_0B (0xCD) - Frequency B, Control Register 0 ........................................................... 101 FREQ_1A (0xCB) - Frequency A, Control Register 1........................................................... 100 FREQ_1B (0xCE) - Frequency B, Control Register 1............................................................ 101
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 130 of 133
Chipcon
SmartRF a CC1010
FREQ_2A (0xCC) - Frequency A, Control Register 2 .......................................................... 100 FREQ_2B (0xCF) - Frequency B, Control Register 2............................................................ 101 FSCTRL (0xEC) - Frequency Synthesiser Control Register ................................................. 119 FSDELAY (0xE9) - Frequency Shaping Delay Control Register ........................................... 118 FSEP0 (0xEA) - Frequency Separation Control Register 0................................................... 101 FSEP1 (0xEB) - Frequency Separation Control Register 1................................................... 101 FSHAPEn (0xF1 - 0xF7), n1..7 - Frequency Shaping Register n ....................................... 118 IE (0xA8) - Interrupt Enable Register....................................................................................... 27 IP (0xB8) - Interrupt Priority Register....................................................................................... 29 LOCK (0xE4) - PLL Lock Register ......................................................................................... 102 MATCH (0xDC) - Match Capacitor Array Control Register ................................................... 112 MODEM0 (0xDB) - Modem Control Register 0........................................................................ 88 MODEM1 (0xDA) - Modem Control Register 1........................................................................ 95 MODEM2 (0xD9) - Modem Control Register 2 ........................................................................ 95 MPAGE (0x92) - Memory Page Select Register...................................................................... 20 P0 (0x80) - Port 0 Data Register ............................................................................................. 45 P0DIR (0xA4) - Port 0 Direction Register ................................................................................ 46 P1 (0x90) - Port 1 Data Register ............................................................................................. 45 P1DIR (0xA5) - Port 1 Direction Register ................................................................................ 46 P2 (0xA0) - Port 2 Data Register ............................................................................................. 46 P2DIR (0xA6) - Port 2 Direction Register ................................................................................ 47 P3 (0xB0) - Port 3 Data Register ............................................................................................. 46 P3DIR (0xA7) - Port 3 Direction Register ................................................................................ 47 PA_POW (0xE2) - PA Output Power Control Register.......................................................... 114 PCON (0x87) - Power Control Register ................................................................................... 32 PDET (0xD3) - Preamble Detection Control Register ............................................................. 96 PLL (0xE3) - PLL Control Register ........................................................................................ 101 PRESCALER (0xE6) - Prescaler Control Register ................................................................ 119 PSW (0xD0) - Program Status Word ....................................................................................... 21 RADRH (0xBB) - Replacement address, high byte ................................................................. 42 RADRL (0xBA) - Replacement address, low byte ................................................................... 42 RANCON (0xC7) - Random Bit Generator Control Register ................................................... 74 RDATA (0xB9) - Replacement Data ........................................................................................ 42 RESERVED (0xE7) - Reserved register, used by Chipcon debugger software...................... 42 RFBUF (0xC9) - RF Data Buffer .............................................................................................. 90
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 131 of 133
Chipcon
SmartRF a CC1010
RFCON (0xC2) - RF Control Register ..................................................................................... 95 RFMAIN (0xC8) - RF Main Control Register ........................................................................... 84 RTCON (0xED) - Realtime Clock Control Register ................................................................. 61 SBUF0 (0x99) - Serial Port 0, data buffer................................................................................ 63 SBUF1 (0xC1) - Serial Port 1, data buffer .............................................................................. 63 SCON0 (0x98) - Serial Port 0 Control Register ....................................................................... 63 SCON1 (0xC0) - Serial Port 1 Control Register....................................................................... 64 SP (0x81) - Stack Pointer ........................................................................................................ 21 SPCR (0xA1) - SPI Control Register ....................................................................................... 67 SPDR (0xA2) - SPI Data Register ........................................................................................... 67 SPSR (0xA3) - SPI Status Register ......................................................................................... 68 T2 (0xAC) - Timer 2 Low byte counter value ........................................................................... 55 T2PRE (0xAA) - Timer 2 Prescaler Control ............................................................................. 55 T3 (0xAD) - Timer 3 Low byte counter value ........................................................................... 55 T3PRE (0xAB) - Timer 3 Prescaler Control ............................................................................. 55 TCON (0x88) - Timer / Counter 0 and 1 control register ......................................................... 50 TCON2 (0xA9) - Timer Control register 2 ................................................................................ 54 TEST0 (0xF9) - PLL Test Register 0 .................................................................................... 107 TEST1 (0xFA) - PLL Test Register 1 .................................................................................... 107 TEST2 (0xFB) - PLL Test Register 2 .................................................................................... 107 TEST3 (0xFC) - PLL Test Register 3 .................................................................................... 107 TEST4 (0xFD) - PLL Test Register 4 .................................................................................... 107 TEST5 (0xFE) - PLL Test Register 5 .................................................................................... 107 TEST6 (0xFF) - PLL Test Register 6 .................................................................................... 106 TESTMUX (0xEF) - Test Multiplexer Control Register (for prototype testing)....................... 119 TH0 (0x8C) - Timer / Counter 0 High byte counter value ........................................................ 48 TH1 (0x8D) - Timer / Counter 1 High byte counter value ........................................................ 48 TL0 (0x8A) - Timer / Counter 0 Low byte counter value.......................................................... 48 TL1 (0x8B) - Timer / Counter 1 Low byte counter value.......................................................... 48 TMOD (0x89) - Timer / Counter 0 and 1 Mode register........................................................... 49 WDT (0xD2) - Watchdog Timer Control Register .................................................................... 58 X32CON (0xD1) - 32.768 kHz Crystal Oscillator Control Register.......................................... 33
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 132 of 133
Chipcon
Ordering Information
Ordering part number CC1010 CC1010/T&R CC1010DK-433 CC1010DK-868
CC1010SK
SmartRF a CC1010
Description Single Chip RF Transceiver with MCU Single Chip RF Transceiver with MCU CC1010 Development Kit, 433 MHz CC1010 Development Kit, 868/915 MHz CC1010 Sample Kit (5 pcs)
MOQ 160 (tray) 1500 (tape and reel) 1 1
1
MOQ = Minimum Order Quantity
Contact information Chipcon AS Gaustadalleen 21 N-0349 Oslo NORWAY Telephone Fax E-mail Web site : : : : (+47) 22 95 85 44 (+47) 22 95 85 46 wireless@chipcon.com (information about RF-IC products) support@chipcon.com (support on our standard products) http://www.chipcon.com
General Information
Chipcon AS believes the information contained herein is correct and accurate at the time of this printing. However, Chipcon AS reserves the right to make changes to this product without notice. Chipcon AS does not assume any responsibility for the use of the described product. The latest updates are available at the Chipcon website or by contacting Chipcon directly.
SmartRFa is a registered trademark of Chipcon AS. SmartRFa is Chipcon's RF technology platform with RF library cells, modules and design expertise. Based on SmartRFa technology Chipcon develops standard component RF circuits as well as full custom ASICs based on customer requirements and this technology.
All other trademarks, registered trademarks and product names are the sole property of their respective owners.
Disclaimer
This Chipcon product contains Flash memory code protection. However, Chipcon does not guarantee the security of this protection. Chipcon customers using or selling these products with program code do so at their own risk and agree to fully indemnify Chipcon AS for any damages resulting from the use or sale of such products. Chipcon believes that the Flash memory protection used in this product is one of the most secure of its kind in the market today when used in the intended manner and under normal conditions. However, there are dishonest and possibly illegal methods to breach the code protection feature. All of these methods, to our knowledge, require using the product in a manner outside the operating specifications. The person doing so may be engaged in theft of intellectual property. Neither Chipcon nor any other semiconductor manufacturer can guarantee the security of their code protection. Code protection does not mean that we are guaranteeing the product as "unbreakable". This Chipcon product contains hardware DES encryption. Chipcon does not guarantee the security of the key protection or the security of the encryption scheme. Chipcon customers using or selling products with DES do so at their own risk and agree to fully indemnify Chipcon AS for any damages resulting from the use or sale of such products.
Life Support Policy
This Chipcon product is not designed for use in life support appliances, devices, or other systems where malfunction can reasonably be expected to result in significant personal injury to the user, or as a critical component in any life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Chipcon AS customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Chipcon AS for any damages resulting from any improper use or sale.
Chipcon AS
SmartRFa CC1010 PRELIMINARY Datasheet (rev. 1.0) 2002-09-18
Page 133 of 133

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